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    INTEGRATED CIRCUITS AND METHODS OF FORMING THE SAME
    4.
    发明申请
    INTEGRATED CIRCUITS AND METHODS OF FORMING THE SAME 有权
    集成电路及其形成方法

    公开(公告)号：US20110298551A1

    公开(公告)日：2011-12-08

    申请号：US12795734

    申请日：2010-06-08

    Applicant: Hsiao-Tsung YEN ,  Hsien-Pin HU ,  Jhe-Ching LU ,  Chin-Wei KUO ,  Ming-Fa CHEN ,  Sally LIU

    Inventor： Hsiao-Tsung YEN ,  Hsien-Pin HU ,  Jhe-Ching LU ,  Chin-Wei KUO ,  Ming-Fa CHEN ,  Sally LIU

    IPC: H03B5/12 ,  H01L21/329 ,  H01L29/93

    CPC classification number: H01L27/016 ,  H01L29/93

    Abstract: A three-dimensional integrated circuit includes a semiconductor substrate where the substrate has an opening extending through a first surface and a second surface of the substrate and where the first surface and the second surface are opposite surfaces of the substrate. A conductive material substantially fills the opening of the substrate to form a conductive through-substrate-via (TSV). An active circuit is disposed on the first surface of the substrate, an inductor is disposed on the second surface of the substrate and the TSV is electrically coupled to the active circuit and the inductor. The three-dimensional integrated circuit may include a varactor formed from a dielectric layer formed in the opening of the substrate such that the conductive material is disposed adjacent the dielectric layer and an impurity implanted region disposed surrounding the TSV such that the dielectric layer is formed between the impurity implanted region and the TSV.

    Abstract translation: 三维集成电路包括半导体衬底，其中衬底具有延伸穿过衬底的第一表面和第二表面的开口，并且第一表面和第二表面与衬底相对的表面。 导电材料基本上填充衬底的开口以形成导电的通过衬底通孔（TSV）。 有源电路设置在衬底的第一表面上，电感器设置在衬底的第二表面上，并且TSV电耦合到有源电路和电感器。 三维集成电路可以包括由形成在基板的开口中的电介质层形成的变容二极管，使得导电材料邻近介电层设置，以及设置在TSV周围的杂质注入区域，使得介电层形成在 杂质注入区和TSV。

    Integrated circuits and methods of forming the same
    9.
    发明授权
    Integrated circuits and methods of forming the same 有权
    集成电路及其形成方法

    公开(公告)号：US08362591B2

    公开(公告)日：2013-01-29

    申请号：US12795734

    申请日：2010-06-08

    Applicant: Hsiao-Tsung Yen ,  Hsien-Pin Hu ,  Jhe-Ching Lu ,  Chin-Wei Kuo ,  Ming-Fa Chen ,  Sally Liu

    Inventor： Hsiao-Tsung Yen ,  Hsien-Pin Hu ,  Jhe-Ching Lu ,  Chin-Wei Kuo ,  Ming-Fa Chen ,  Sally Liu

    IPC: H01L29/93

    CPC classification number: H01L27/016 ,  H01L29/93

    Abstract: A three-dimensional integrated circuit includes a semiconductor substrate where the substrate has an opening extending through a first surface and a second surface of the substrate and where the first surface and the second surface are opposite surfaces of the substrate. A conductive material substantially fills the opening of the substrate to form a conductive through-substrate-via (TSV). An active circuit is disposed on the first surface of the substrate, an inductor is disposed on the second surface of the substrate and the TSV is electrically coupled to the active circuit and the inductor. The three-dimensional integrated circuit may include a varactor formed from a dielectric layer formed in the opening of the substrate such that the conductive material is disposed adjacent the dielectric layer and an impurity implanted region disposed surrounding the TSV such that the dielectric layer is formed between the impurity implanted region and the TSV.

    Abstract translation: 三维集成电路包括半导体衬底，其中衬底具有延伸穿过衬底的第一表面和第二表面的开口，并且其中第一表面和第二表面是与衬底相对的表面。 导电材料基本上填充衬底的开口以形成导电的通过衬底通孔（TSV）。 有源电路设置在衬底的第一表面上，电感器设置在衬底的第二表面上，并且TSV电耦合到有源电路和电感器。 三维集成电路可以包括由形成在基板的开口中的电介质层形成的变容二极管，使得导电材料邻近介电层设置，以及设置在TSV周围的杂质注入区域，使得介电层形成在 杂质注入区和TSV。

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