公开(公告)号：US08772952B2

公开(公告)日：2014-07-08

申请号：US12889023

申请日：2010-09-23

Applicant: Masatoshi Yasunaga ,  Hironori Matsushima ,  Kenya Hironaga ,  Soshi Kuroda

Inventor： Masatoshi Yasunaga ,  Hironori Matsushima ,  Kenya Hironaga ,  Soshi Kuroda

IPC: H01L29/40

CPC classification number: H01L24/85 ,  H01L21/561 ,  H01L22/32 ,  H01L23/3128 ,  H01L23/49866 ,  H01L24/03 ,  H01L24/04 ,  H01L24/05 ,  H01L24/27 ,  H01L24/43 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/02166 ,  H01L2224/0392 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05018 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/32145 ,  H01L2224/43 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/48482 ,  H01L2224/48499 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48724 ,  H01L2224/48844 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/49431 ,  H01L2224/85051 ,  H01L2224/85205 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/10162 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/00014 ,  H01L2224/85 ,  H01L2924/20752 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/48824 ,  H01L2224/48744 ,  H01L2924/20758 ,  H01L2924/2075 ,  H01L2924/00015

Abstract: To improve reliability of a semiconductor device in which wire bonding using a wire made of copper is performed. A semiconductor device is configured so that one of end parts (wide width part) of a copper wire is joined via a bump on a pad (electrode pad) formed over a main surface (first main surface) of a semiconductor chip of the semiconductor device. The bump is made of gold, which is a metal material having a hardness lower than that of copper, and the width of the bump is narrower than the width of the wide width part of the wire.

Abstract translation: 为了提高使用由铜制成的线进行引线接合的半导体器件的可靠性。 半导体器件被配置为使得铜线的端部（宽宽度部分）中的一个通过形成在半导体器件的半导体芯片的主表面（第一主表面）上的焊盘（电极焊盘）上的凸块接合 。 凸起由金制成，其是具有低于铜的硬度的金属材料，并且凸块的宽度比电线的宽幅部分的宽度窄。

公开(公告)号：US08334172B2

公开(公告)日：2012-12-18

申请号：US13023976

申请日：2011-02-09

Applicant: Soshi Kuroda ,  Masatoshi Yasunaga ,  Hironori Matsushima ,  Kenya Hironaga

Inventor： Soshi Kuroda ,  Masatoshi Yasunaga ,  Hironori Matsushima ,  Kenya Hironaga

IPC: H01L21/786 ,  H01L21/60 ,  H01L21/56 ,  H01L21/58 ,  H01L21/00

CPC classification number: H01L24/48 ,  H01L21/4853 ,  H01L23/295 ,  H01L23/296 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/544 ,  H01L24/45 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L2223/54406 ,  H01L2223/54486 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32013 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/48599 ,  H01L2224/48644 ,  H01L2224/73265 ,  H01L2224/83101 ,  H01L2224/83192 ,  H01L2224/838 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2224/85444 ,  H01L2224/92 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/1579 ,  H01L2924/181 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2224/92247 ,  H01L2924/00 ,  H01L2224/78 ,  H01L2924/00012

Abstract: Technology capable of preventing the deterioration of the reliability of semiconductor devices caused by the gasification of a part of the material constituting a wiring substrate is provided. A wiring layer constituting a circuit pattern is formed over each of the front and rear surfaces of a glass epoxy substrate, and after the formation of a solder resist covering the wiring layer while exposing a part of the wiring layer and prior to a heat treatment (first heat treatment) at 100° C. to 150° C. for dehumidification, a heat treatment (second heat treatment) at 160° C. to 230° C. for gasifying and discharging an organic solvent contained in the material constituting a wiring substrate is performed for the wiring substrate.

Abstract translation: 提供了能够防止由构成布线基板的材料的一部分的气化引起的半导体器件的可靠性劣化的技术。 构成电路图案的布线层形成在玻璃环氧树脂基板的前表面和后表面之上，并且在暴露一部分布线层并且在热处理之前形成覆盖布线层的阻焊剂之后 第一热处理）在100℃至150℃下进行除湿，在160℃至230℃下进行热处理（第二热处理），用于气化和排出构成布线基板的材料中所含的有机溶剂 对布线基板进行。

公开(公告)号：US20120015040A1

公开(公告)日：2012-01-19

申请号：US12920983

申请日：2009-03-02

Applicant: Akira Takashima ,  Hironori Matsushima ,  Shuo Geng

Inventor： Akira Takashima ,  Hironori Matsushima ,  Shuo Geng

IPC: A61K35/14 ,  C12Q1/02 ,  C12Q1/68 ,  A61P29/00 ,  A61P31/00 ,  A61P31/12 ,  A61P37/00 ,  A61P37/06 ,  C12N5/0784 ,  G01N33/566

CPC classification number: C12N5/0639 ,  A61K35/15 ,  A61K2035/124 ,  C12N2501/22 ,  G01N33/5047 ,  G01N33/56972 ,  G01N2500/10 ,  G01N2800/24

Abstract: Dendritic cell precursor populations, dendritic cell populations derived therefrom, methods for isolating, expanding and using are disclosed.

Abstract translation: 公开了树突状细胞前体种群，从其衍生的树突细胞群体，分离，扩增和使用的方法。

公开(公告)号：US07725847B2

公开(公告)日：2010-05-25

申请号：US10586908

申请日：2004-11-01

Applicant: Akihiro Goto ,  Hironori Matsushima ,  Hiroshige Ogawa ,  Yoshio Matsuda

Inventor： Akihiro Goto ,  Hironori Matsushima ,  Hiroshige Ogawa ,  Yoshio Matsuda

IPC: G06F17/50

CPC classification number: G06F17/5068 ,  H01L23/3128 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/49052 ,  H01L2224/49171 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A design support apparatus supports wiring design for bond wires that connect a semiconductor chip and an interposer. The design support apparatus includes a creating unit that creates simulated design data simulating occurrence of fluctuation in an arrangement position of a semiconductor chip on an interposer and occurrence of fluctuation in bond wire connection terminal positions of the interposer, and an analyzing unit that analyzes, based on the simulated design data, deficiencies in manufacturing of semiconductor devices due to the fluctuation in the arrangement position of the semiconductor chip on the interposer and the fluctuation in the bond wire connection terminal positions of the interposer.

Abstract translation: 设计支持设备支持连接半导体芯片和插入器的接合线的布线设计。 设计支持装置包括：创建单元，其创建模拟设计数据，模拟在插入器上的半导体芯片的布置位置的波动的发生以及插入器的接合线连接端子位置的波动的发生;以及分析单元， 关于模拟设计数据，由于插入件上的半导体芯片的布置位置的波动以及插入器的接合线连接端子位置的波动引起的半导体器件的制造缺陷。

公开(公告)号：US06984882B2

公开(公告)日：2006-01-10

申请号：US10348013

申请日：2003-01-22

Applicant: Hironori Matsushima

Inventor： Hironori Matsushima

IPC: H01L23/02

CPC classification number: H01L24/06 ,  H01L23/5387 ,  H01L24/02 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L25/065 ,  H01L25/0652 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05599 ,  H01L2224/32145 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48599 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/10161 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/00 ,  H01L2924/00012

Abstract: There is provided a semiconductor device comprising a semiconductor chip and an electronic part disposed adjacent to each other, wherein a terminal is provided on the side of each of the semiconductor chip and the electronic part, and the terminal is electrically connected to the other terminal in the state where the sides of the semiconductor chip and the electronic part approach to each other. Thereby, the size of the entire semiconductor device can be reduced, and the wiring path can be shortened significantly to improve electrical properties.

Abstract translation: 提供了一种包括半导体芯片和彼此相邻布置的电子部件的半导体器件，其中，在半导体芯片和电子部件的每一侧设置有端子，并且端子与另一个端子电连接 半导体芯片的侧面和电子部件彼此接近的状态。 由此，可以减小整个半导体器件的尺寸，并且可以显着地缩短布线路径以改善电气性能。

公开(公告)号：US5920770A

公开(公告)日：1999-07-06

申请号：US837960

申请日：1997-04-14

Applicant: Masatoshi Yasunaga ,  Shin Nakao ,  Shinji Baba ,  Mitsuyasu Matsuo ,  Hironori Matsushima

Inventor： Masatoshi Yasunaga ,  Shin Nakao ,  Shinji Baba ,  Mitsuyasu Matsuo ,  Hironori Matsushima

IPC: H01L21/60 ,  H01L21/56 ,  H01L21/68 ,  H01L23/12 ,  H01L23/28 ,  H01L23/31 ,  H01L23/32 ,  H01L23/485 ,  H01L25/10 ,  H05K3/30 ,  H05K3/34 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC classification number: H01L21/568 ,  H01L21/565 ,  H01L21/6835 ,  H01L23/3107 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L25/10 ,  H01L25/105 ,  H05K3/303 ,  H01L2224/0231 ,  H01L2224/0233 ,  H01L2224/02333 ,  H01L2224/02335 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/1131 ,  H01L2224/11332 ,  H01L2224/11334 ,  H01L2224/1147 ,  H01L2224/1191 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16105 ,  H01L2224/16108 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/4813 ,  H01L2224/48624 ,  H01L2224/48724 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/812 ,  H01L2224/81801 ,  H01L2224/83104 ,  H01L2225/1005 ,  H01L2225/1035 ,  H01L2225/107 ,  H01L24/45 ,  H01L24/48 ,  H01L24/81 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01057 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/07802 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/351 ,  H05K2201/09909 ,  H05K2201/10454 ,  H05K2201/10484 ,  H05K2201/2036 ,  H05K3/3442 ,  Y02P70/613

Abstract: Bonding pads are formed on a main surface of a semiconductor chip. An insulating layer having openings located on the bonding pads is formed on the main surface of the semiconductor chip. Base metal layers are formed on the bonding pads. A buffer coat film having a portion laid on a periphery of the base metal layer is formed on the insulating layer. Connection layers are formed on the base metal layers. First conductors are formed on the connection layers. A seal resin exposing only top surfaces of the first conductors is formed. Lumpish second conductors are formed on the top surfaces of the first conductor. Thereby, a resin seal semiconductor package can be made compact and it has improved electrical characteristics and high reliability.

Abstract translation: 接合焊盘形成在半导体芯片的主表面上。 在半导体芯片的主表面上形成具有位于接合焊盘上的开口的绝缘层。 在接合焊盘上形成基底金属层。 在绝缘层上形成具有放置在基底金属层周围的部分的缓冲涂膜。 连接层形成在基底金属层上。 第一导体形成在连接层上。 形成仅露出第一导体的顶表面的密封树脂。 在第一导体的顶表面上形成笨重的第二导体。 因此，可以使树脂密封半导体封装紧凑并且具有改善的电特性和高可靠性。

公开(公告)号：US20110074019A1

公开(公告)日：2011-03-31

申请号：US12889023

申请日：2010-09-23

Applicant: Masatoshi YASUNAGA ,  Hironori Matsushima ,  Kenya Hironaga ,  Soshi Kuroda

Inventor： Masatoshi YASUNAGA ,  Hironori Matsushima ,  Kenya Hironaga ,  Soshi Kuroda

IPC: H01L23/48

CPC classification number: H01L24/85 ,  H01L21/561 ,  H01L22/32 ,  H01L23/3128 ,  H01L23/49866 ,  H01L24/03 ,  H01L24/04 ,  H01L24/05 ,  H01L24/27 ,  H01L24/43 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/02166 ,  H01L2224/0392 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05018 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/32145 ,  H01L2224/43 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/48482 ,  H01L2224/48499 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48724 ,  H01L2224/48844 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/49431 ,  H01L2224/85051 ,  H01L2224/85205 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/10162 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/00014 ,  H01L2224/85 ,  H01L2924/20752 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/48824 ,  H01L2224/48744 ,  H01L2924/20758 ,  H01L2924/2075 ,  H01L2924/00015

Abstract: To improve reliability of a semiconductor device in which wire bonding using a wire made of copper is performed. A semiconductor device is configured so that one of end parts (wide width part) of a copper wire is joined via a bump on a pad (electrode pad) formed over a main surface (first main surface) of a semiconductor chip of the semiconductor device. The bump is made of gold, which is a metal material having a hardness lower than that of copper, and the width of the bump is narrower than the width of the wide width part of the wire.

Abstract translation: 为了提高使用由铜制成的线进行引线接合的半导体器件的可靠性。 半导体器件被配置为使得铜线的端部（宽宽度部分）中的一个通过形成在半导体器件的半导体芯片的主表面（第一主表面）上的焊盘（电极焊盘）上的凸块接合 。 凸起由金制成，其是具有低于铜的硬度的金属材料，并且凸块的宽度比电线的宽幅部分的宽度窄。

公开(公告)号：US06515360B2

公开(公告)日：2003-02-04

申请号：US09495906

申请日：2000-02-02

Applicant: Hironori Matsushima ,  Yoshihiro Tomita

Inventor： Hironori Matsushima ,  Yoshihiro Tomita

IPC: H01L2312

CPC classification number: H01L23/10 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/01019 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/16195 ,  H01L2924/16315 ,  H01L2924/00012

Abstract: A semiconductor chip is attached on a package substrate so as to be electrically connected to it and sealed. A ring member is attached to the package substrate and surrounds the semiconductor chip. A lid member is attached to the ring member and covers the semiconductor chip. The lid member is formed so as to be able to be removed from the ring member without impairing the attachment of the ring member to the package substrate.

Abstract translation: 将半导体芯片安装在封装基板上，以便与其电连接并密封。 环形构件附接到封装衬底并且围绕半导体芯片。 盖构件附接到环构件并覆盖半导体芯片。 盖构件形成为能够从环构件移除，而不会妨碍环构件附接到封装衬底。

公开(公告)号：US20120061850A1

公开(公告)日：2012-03-15

申请号：US13231856

申请日：2011-09-13

Applicant: Soshi KURODA ,  Kenya Hironaga ,  Hironori Matsushima ,  Masatoshi Yasunaga ,  Akira Yamazaki

Inventor： Soshi KURODA ,  Kenya Hironaga ,  Hironori Matsushima ,  Masatoshi Yasunaga ,  Akira Yamazaki

IPC: H01L23/48 ,  H01L21/50

CPC classification number: H01L24/46 ,  H01L21/6836 ,  H01L23/3121 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/743 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/26175 ,  H01L2224/27312 ,  H01L2224/27334 ,  H01L2224/27436 ,  H01L2224/2919 ,  H01L2224/32014 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48011 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83194 ,  H01L2224/83385 ,  H01L2224/838 ,  H01L2224/85 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/10162 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/83 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/3512

Abstract: To achieve a reduction in cost of a semiconductor device, in a common board (a wiring board), a plurality of bonding leads each extend toward the center of the board, and a solder resist film as a die bonding region supporting a minimum chip is coated with a die bonding material. With this, even when a first semiconductor chip as a large chip is mounted, wire bonding can be performed without causing the die bonding material to cover the bonding leads. Thus, development cost can be reduced to reduce the cost of the semiconductor device (LGA).

Abstract translation: 为了实现半导体器件的成本降低，在公共板（布线板）中，多个接合引线各自朝向基板的中心延伸，并且作为支撑最小芯片的芯片接合区域的阻焊膜为 涂有芯片接合材料。 由此，即使安装作为大芯片的第一半导体芯片，也可以在不使芯片接合材料覆盖接合引线的情况下进行引线接合。 因此，可以降低开发成本以降低半导体器件（LGA）的成本。

公开(公告)号：US06232652B1

公开(公告)日：2001-05-15

申请号：US09447675

申请日：1999-11-23

Applicant: Hironori Matsushima

Inventor： Hironori Matsushima

IPC: H01L2304

CPC classification number: H01L23/055 ,  H01L2224/16225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/15311 ,  H01L2924/16195

Abstract: In a semiconductor device, a semiconductor chip is mounted on a planar substrate approximately at the center and a hollow cavity for housing the semiconductor chip is formed by laminating an annular ring member, annular adhesive tapes, and a heat spreader plate on the substrate. A slit is formed in the adhesive tape or the ring member to provide an air vent.

Abstract translation: 在半导体装置中，半导体芯片安装在大致中央的平面基板上，通过在基板上层叠环状的环状部件，环状的胶带和散热板，形成用于容纳半导体芯片的中空腔体。 在粘合带或环形构件中形成狭缝以提供通风口。