公开(公告)号：US20120061850A1

公开(公告)日：2012-03-15

申请号：US13231856

申请日：2011-09-13

Applicant: Soshi KURODA ,  Kenya Hironaga ,  Hironori Matsushima ,  Masatoshi Yasunaga ,  Akira Yamazaki

Inventor： Soshi KURODA ,  Kenya Hironaga ,  Hironori Matsushima ,  Masatoshi Yasunaga ,  Akira Yamazaki

IPC: H01L23/48 ,  H01L21/50

CPC classification number: H01L24/46 ,  H01L21/6836 ,  H01L23/3121 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/743 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/26175 ,  H01L2224/27312 ,  H01L2224/27334 ,  H01L2224/27436 ,  H01L2224/2919 ,  H01L2224/32014 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48011 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83194 ,  H01L2224/83385 ,  H01L2224/838 ,  H01L2224/85 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/10162 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/83 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/3512

Abstract: To achieve a reduction in cost of a semiconductor device, in a common board (a wiring board), a plurality of bonding leads each extend toward the center of the board, and a solder resist film as a die bonding region supporting a minimum chip is coated with a die bonding material. With this, even when a first semiconductor chip as a large chip is mounted, wire bonding can be performed without causing the die bonding material to cover the bonding leads. Thus, development cost can be reduced to reduce the cost of the semiconductor device (LGA).

Abstract translation: 为了实现半导体器件的成本降低，在公共板（布线板）中，多个接合引线各自朝向基板的中心延伸，并且作为支撑最小芯片的芯片接合区域的阻焊膜为 涂有芯片接合材料。 由此，即使安装作为大芯片的第一半导体芯片，也可以在不使芯片接合材料覆盖接合引线的情况下进行引线接合。 因此，可以降低开发成本以降低半导体器件（LGA）的成本。

公开(公告)号：US06476502B2

公开(公告)日：2002-11-05

申请号：US09517050

申请日：2000-03-02

Applicant: Satoshi Yamada ,  Michitaka Kimura ,  Masatoshi Yasunaga

Inventor： Satoshi Yamada ,  Michitaka Kimura ,  Masatoshi Yasunaga

IPC: H01L2348

CPC classification number: H01L25/0657 ,  H01L25/0652 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06555 ,  H01L2225/06558 ,  H01L2225/06562 ,  H01L2225/06582 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/05552

Abstract: An insulating resin sheet made from a thermosetting resin is provided on an insulating substrate in such a manner as to cover bonding pads provided on the insulating substrate. A lower chip is set on the insulating substrate in such a manner that bonding bumps connected to inner connection terminals of the lower chip break the insulating resin sheet 24 to be in contact with the bonding pads. The insulating resin sheet is thermally cured and subsequently the bonding bumps are melted.

Abstract translation: 在绝缘基板上设置由热固性树脂制成的绝缘树脂片，以覆盖设置在绝缘基板上的接合焊盘。 将下部芯片设置在绝缘基板上，使得与下部芯片的内部连接端子连接的接合凸块将绝缘树脂片材24与接合焊盘接触。 绝缘树脂板被热固化，随后粘合凸块熔化。

公开(公告)号：US5096853A

公开(公告)日：1992-03-17

申请号：US664119

申请日：1991-03-04

Applicant: Masatoshi Yasunaga ,  Masanobu Kohara

Inventor： Masatoshi Yasunaga ,  Masanobu Kohara

IPC: H01L21/56 ,  H01L23/495

CPC classification number: H01L21/565 ,  H01L23/49503 ,  H01L24/50 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/181 ,  Y10T29/49121

Abstract: A lead frame includes a die pad for mounting thereon a semiconductor chip having a plurality of electrodes, a plurality of leads for electrical connection with the plurality of electrodes of the semiconductor chip, an outer frame disposed on the periphery of the die pad for supporting the die pad and the plurality of leads, and a resin guide portion extending to the vicinity of the die pad from the outer frame for guiding a molten resin over and under the semiconductor chip during resin packaging. A semiconductor device manufacturing method includes mounting a semiconductor chip having electrodes on a substrate having a resin guiding portion for guiding a resin over and under the semiconductor chip during resin packaging; electrically connecting leads on the substrate to the electrodes positioning the semiconductor chip and the substrate between a pair of mold halves injecting a molten resin into the mold and solidifying the resin.

公开(公告)号：US08605277B2

公开(公告)日：2013-12-10

申请号：US13244434

申请日：2011-09-24

Applicant: Satoshi Yamada ,  Takashi Karashima ,  Kenya Hironaga ,  Masatoshi Yasunaga ,  Yuji Fujimoto

Inventor： Satoshi Yamada ,  Takashi Karashima ,  Kenya Hironaga ,  Masatoshi Yasunaga ,  Yuji Fujimoto

IPC: G01N21/00

CPC classification number: G01N21/95684 ,  G01B11/306 ,  G01N21/93 ,  H01L23/3128 ,  H01L2224/48227 ,  H01L2924/01322 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/00

Abstract: Reliability of a semiconductor device is improved. In a flatness inspection of BGA (semiconductor device), there is formed a flatness standard where a permissible range in the direction of (+) of flatness at normal temperature is smaller than a permissible range in the direction of (−). With use of the above flatness standard, a flatness inspection of the semiconductor device at normal temperature is performed to determine whether the mounted item is non-defective or defective. With the above process, defective mounting caused by a package warp when heated during reflow soldering etc. is reduced and reliability of BGA is improved. At the same time, flatness management of a substrate-type semiconductor device with better consideration of a mounting state can be performed.

Abstract translation: 提高了半导体器件的可靠性。 在BGA（半导体器件）的平坦度检查中，形成了平坦度标准，其中常温平面度（+）方向上的允许范围小于（ - ）方向的允许范围。 使用上述平面度标准，进行半导体器件在常温下的平坦度检查，以确定安装的物品是否是有缺陷的或有缺陷的。 通过上述处理，在回流焊接等期间加热时由包装翘曲引起的安装不良导致BGA的可靠性提高。 同时，可以进行更好地考虑安装状态的基板型半导体器件的平坦度管理。

公开(公告)号：US20120081702A1

公开(公告)日：2012-04-05

申请号：US13244434

申请日：2011-09-24

Applicant: Satoshi YAMADA ,  Takashi KARASHIMA ,  Kenya HIRONAGA ,  Masatoshi YASUNAGA ,  Yuji FUJIMOTO

Inventor： Satoshi YAMADA ,  Takashi KARASHIMA ,  Kenya HIRONAGA ,  Masatoshi YASUNAGA ,  Yuji FUJIMOTO

IPC: G01N21/00

CPC classification number: G01N21/95684 ,  G01B11/306 ,  G01N21/93 ,  H01L23/3128 ,  H01L2224/48227 ,  H01L2924/01322 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/00

Abstract: Reliability of a semiconductor device is improved. In a flatness inspection of BGA (semiconductor device), there is formed a flatness standard where a permissible range in the direction of (+) of flatness at normal temperature is smaller than a permissible range in the direction of (−). With use of the above flatness standard, a flatness inspection of the semiconductor device at normal temperature is performed to determine whether the mounted item is non-defective or defective. With the above process, defective mounting caused by a package warp when heated during reflow soldering etc. is reduced and reliability of BGA is improved. At the same time, flatness management of a substrate-type semiconductor device with better consideration of a mounting state can be performed.

Abstract translation: 提高了半导体器件的可靠性。 在BGA（半导体器件）的平坦度检查中，形成了平坦度标准，其中常温平面度（+）方向上的允许范围小于（ - ）方向的允许范围。 使用上述平面度标准，进行半导体器件在常温下的平坦度检查，以确定安装的物品是否是有缺陷的或有缺陷的。 通过上述处理，在回流焊接等期间加热时由包装翘曲引起的安装不良导致BGA的可靠性提高。 同时，可以进行更好地考虑安装状态的基板型半导体器件的平坦度管理。

公开(公告)号：US20110201155A1

公开(公告)日：2011-08-18

申请号：US13023976

申请日：2011-02-09

Applicant: Soshi Kuroda ,  Masatoshi Yasunaga ,  Hironori Matsushima ,  Kenya Hironaga

Inventor： Soshi Kuroda ,  Masatoshi Yasunaga ,  Hironori Matsushima ,  Kenya Hironaga

IPC: H01L21/786 ,  H01L21/60 ,  H01L21/56 ,  H01L21/58 ,  H01L21/00

CPC classification number: H01L24/48 ,  H01L21/4853 ,  H01L23/295 ,  H01L23/296 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/544 ,  H01L24/45 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L2223/54406 ,  H01L2223/54486 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32013 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/48599 ,  H01L2224/48644 ,  H01L2224/73265 ,  H01L2224/83101 ,  H01L2224/83192 ,  H01L2224/838 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2224/85444 ,  H01L2224/92 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/1579 ,  H01L2924/181 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2224/92247 ,  H01L2924/00 ,  H01L2224/78 ,  H01L2924/00012

Abstract: To provide a technology capable of preventing the deterioration of the reliability of semiconductor devices caused by the gasification of a part of components of the material constituting a wiring substrate.A wiring layer constituting a circuit pattern is formed over each of the front and rear surfaces of a glass epoxy substrate, and after the formation of a solder resist covering the wiring layer while exposing a part of the wiring layer and prior to a heat treatment (first heat treatment) at 100° C. to 150° C. for dehumidification, a heat treatment (second heat treatment) at 160° C. to 230° C. for gasifying and discharging an organic solvent contained in the material constituting a wiring substrate is performed for the wiring substrate.

Abstract translation: 提供能够防止由构成布线基板的材料的一部分的部件的气化引起的半导体器件的可靠性劣化的技术。 构成电路图案的布线层形成在玻璃环氧树脂基板的前表面和后表面之上，并且在暴露一部分布线层并且在热处理之前形成覆盖布线层的阻焊剂之后 第一热处理）在100℃至150℃下进行除湿，在160℃至230℃下进行热处理（第二热处理），用于气化和排出构成布线基板的材料中所含的有机溶剂 对布线基板进行。

公开(公告)号：US20110076800A1

公开(公告)日：2011-03-31

申请号：US12834937

申请日：2010-07-13

Applicant: Tatsuya HIRAI ,  Tomoaki HASHIMOTO ,  Takashi KIKUCHI ,  Masatoshi YASUNAGA ,  Michiaki SUGIYAMA

Inventor： Tatsuya HIRAI ,  Tomoaki HASHIMOTO ,  Takashi KIKUCHI ,  Masatoshi YASUNAGA ,  Michiaki SUGIYAMA

IPC: H01L21/60

CPC classification number: H01L25/50 ,  H01L21/561 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49833 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/16 ,  H01L2224/05553 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012

Abstract: The reliability of a semiconductor device is improved. A sealing resin (sealed body) is formed between a sub-substrate (first base member) and a base substrate (second base member) that are provided individually and distinctly to be integrated therewith, and then, the sub-substrate is electrically coupled to the second base member. As a means for electrically coupling the sub-substrate to the base substrate, lands (first lands) formed on the sub-substrate and lands (second lands) formed on the base substrate are disposed such that the respective positions thereof are aligned. After through holes are formed from the lands of the sub-substrate toward the lands of the base substrate, a solder member (conductive member) is formed in each of the through holes.

Abstract translation: 提高了半导体器件的可靠性。 在单独且明显地与其一体化设置的子基板（第一基底构件）和基底基板（第二基底构件）之间形成密封树脂（密封体），然后，将辅助基板电耦合到 第二个基础成员。 作为将基板与基板电连接的装置，在基板上形成的焊盘（第一焊盘）和基板上形成的焊盘（第二焊盘）配置成使其各自的位置对齐。 在从底基板的台阶朝向基板的焊盘形成通孔之后，在每个通孔中形成焊料部件（导电部件）。

公开(公告)号：US06856028B1

公开(公告)日：2005-02-15

申请号：US09665415

申请日：2000-09-20

Applicant: Kazuyuki Nakagawa ,  Michitaka Kimura ,  Masatoshi Yasunaga

Inventor： Kazuyuki Nakagawa ,  Michitaka Kimura ,  Masatoshi Yasunaga

IPC: H01L23/12 ,  H01L21/60 ,  H01L23/31 ,  H01L23/495 ,  H01L23/48 ,  H01L23/28 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L23/3114 ,  H01L23/4951 ,  H01L24/48 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/48465 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: In a semiconductor device, a semiconductor element is bonded to an insulating circuit board. A resin layer for bonding the semiconductor element to the insulating circuit board is extended so as to become greater in size than the semiconductor element. Further, the surroundings of the semiconductor element are sealed with resin. Reliability of mounting is improved by alleviating stress developing in a solder joint of the external electrodes of the circuit board.

Abstract translation: 在半导体器件中，将半导体元件接合到绝缘电路板。 用于将半导体元件接合到绝缘电路板的树脂层被延伸以使其尺寸变得比半导体元件大。 此外，半导体元件的周围用树脂密封。 通过减轻电路板的外部电极的焊点中的应力显现来提高安装的可靠性。

公开(公告)号：US06768516B2

公开(公告)日：2004-07-27

申请号：US09732925

申请日：2000-12-11

Applicant: Satoshi Yamada ,  Michitaka Kimura ,  Naoto Ueda ,  Masatoshi Yasunaga

Inventor： Satoshi Yamada ,  Michitaka Kimura ,  Naoto Ueda ,  Masatoshi Yasunaga

IPC: H04N5225

CPC classification number: H04N5/2257 ,  H01L27/14618 ,  H01L27/14625 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/73265 ,  H04N5/2253 ,  H04N5/2254 ,  H01L2924/00014

Abstract: The invention is intended for rendering a CMOS camera compact and less costly. A semiconductor device constituting a CMOS camera system includes a lens unit which includes a wiring board having an image pick-up opening formed therein and a lens, and the lens is provided on one side of the wiring board and positioned opposite the image pick-up opening. An image pick-up semiconductor is provided on the other side of the wiring board, and is positioned opposite the image pick-up opening, and is connected to a connection section of the wiring board by means of flip-chip bonding. An image processing semiconductor is connected by means of flip-chip bonding to another connection section provided on the other side of the wiring board, and processes an image signal output from the image pick-up semiconductor.

Abstract translation: 本发明旨在使CMOS相机紧凑且成本更低。 构成CMOS照相机系统的半导体器件包括透镜单元，该透镜单元包括其中形成有摄像开口的布线板和透镜，并且透镜设置在布线板的一侧并与图像拾取器相对定位 开放 在接线板的另一侧设置摄像半导体，与摄像开口相对设置，并通过倒装芯片接合而与布线基板的连接部连接。 图像处理半导体通过倒装芯片接合连接到设置在布线板的另一侧的另一连接部分，并处理从摄像半导体输出的图像信号。

公开(公告)号：US06544814B1

公开(公告)日：2003-04-08

申请号：US09494361

申请日：2000-01-31

Applicant: Masatoshi Yasunaga ,  Michitaka Kimura ,  Satoshi Yamada

Inventor： Masatoshi Yasunaga ,  Michitaka Kimura ,  Satoshi Yamada

IPC: H01L2144

CPC classification number: H01L24/97 ,  H01L21/561 ,  H01L21/563 ,  H01L21/565 ,  H01L23/3114 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/85399 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2224/92247 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: A plurality of semiconductor chips are mounted on an insulating substrate with bumps and through use of dielectric resin for mounting purposes. The semiconductor chips are sealed with transfer mold resin through a single operation while remaining on the insulating substrate. Then, the plurality of semiconductor chips are separated together with the insulating substrate and the mounting resin into individual semiconductor devices. The productivity and reliability of packaged semiconductor devices is improved.

Abstract translation: 多个半导体芯片安装在具有凸块的绝缘基板上，并且通过使用用于安装目的的电介质树脂。 半导体芯片通过一次操作用传输模塑树脂密封，同时保留在绝缘基板上。 然后，将多个半导体芯片与绝缘基板和安装树脂一起分离成单独的半导体器件。 提高了封装半导体器件的生产率和可靠性。