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    MEMORY DEVICE
    72.
    发明公开
    MEMORY DEVICE 审中-公开

    公开(公告)号：US20230186977A1

    公开(公告)日：2023-06-15

    申请号：US18080021

    申请日：2022-12-13

    Applicant: Unisantis Electronics Singapore Pte. Ltd.

    Inventor： Koji Sakui ,  Riichiro Shirota ,  Nozomu Harada

    IPC: G11C11/4096 ,  H10B12/00 ,  G11C11/4094 ,  G11C16/24

    CPC classification number: G11C11/4096 ,  H10B12/20 ,  G11C11/4094 ,  G11C16/24 ,  G11C2211/401

    Abstract: A memory device includes pages each constituted by memory cells, and a page write operation and a page erase operation are performed. First and second impurity layers and first and second gate conductor layers in each memory cell is connected to a source line, a bit line, a word line, and a driving control line. In a page read operation, page data is read. In the page write and read operations, a selected driving control line is lowered to zero volt at a first reset time, the driving control line is isolated from a driving circuit at a second reset time, thereby putting the driving control line in a zero-volt floating state, and a selected word line is set at zero volt at a third reset time, thereby putting the driving control line in a negative-voltage floating state by capacitive coupling between the word line and the driving control line.

    MEMORY DEVICE USING SEMICONDUCTOR ELEMENT
    74.
    发明公开
    MEMORY DEVICE USING SEMICONDUCTOR ELEMENT 审中-公开

    公开(公告)号：US20240321343A1

    公开(公告)日：2024-09-26

    申请号：US18609198

    申请日：2024-03-19

    Applicant: Unisantis Electronics Singapore Pte. Ltd.

    Inventor： Koji SAKUI ,  Yoshihisa IWATA ,  Masakazu KAKUMU ,  Nozomu HARADA

    IPC: G11C11/4096 ,  G11C5/06 ,  G11C11/4094 ,  H10B12/00

    CPC classification number: G11C11/4096 ,  G11C5/063 ,  G11C11/4094 ,  H10B12/20 ,  H10B12/50

    Abstract: In a memory device, a page is composed of memory cells arranged in rows, and pages are arranged in columns in plan view on a substrate. Each memory cell has a semiconductor base, a first impurity layer and a second impurity layer at both ends in an extension direction of the semiconductor base, and at least two (first and second) gate conductor layers. The first impurity layer is connected to a source line, the second impurity layer to a bit line, one of the first or second gate conductor layer to a selection gate line, and the other to a plate line. Voltages applied to the source line, bit line, selection gate line, and plate line are controlled to perform page erasing and writing operations. A hole group formed by impact ionization is retained within the semiconductor base to have logic storage data that is at least three-valued.

    Memory device using semiconductor elements
    75.
    发明授权
    Memory device using semiconductor elements 有权

    公开(公告)号：US12101925B2

    公开(公告)日：2024-09-24

    申请号：US17739849

    申请日：2022-05-09

    Applicant: Unisantis Electronics Singapore Pte. Ltd.

    Inventor： Nozomu Harada ,  Koji Sakui

    IPC: H10B12/00 ,  G11C11/4097

    CPC classification number: H10B12/20 ,  G11C11/4097

    Abstract: Provided on a substrate are an N+ layer connecting to a source line SL and an N+ layer connecting to a bit line BL that are located at opposite ends of a Si pillar standing in an upright position along the vertical direction, an N layer continuous with the N+ layer, an N layer continuous with the N+ layer, a first gate insulating layer surrounding the Si pillar, a first gate conductor layer surrounding the first gate insulating layer and connecting to a plate line PL, and a second gate conductor layer surrounding a second gate insulating layer surrounding the Si pillar and connecting to a word line WL. A voltage applied to each of the source line SL, the plate line PL, the word line WL, and the bit line BL is controlled to perform a data retention operation for retaining holes, which have been generated through an impact ionization phenomenon or using a gate induced drain leakage current, in a channel region of the Si pillar, and a data erase operation for removing the holes from the channel region.

    Memory device using semiconductor element
    80.
    发明授权
    Memory device using semiconductor element 有权

    公开(公告)号：US12048140B2

    公开(公告)日：2024-07-23

    申请号：US17872310

    申请日：2022-07-25

    Applicant: Unisantis Electronics Singapore Pte. Ltd.

    Inventor： Koji Sakui ,  Nozomu Harada

    IPC: G11C11/4096 ,  G11C11/404 ,  G11C11/4091 ,  H10B12/00

    CPC classification number: H10B12/20 ,  G11C11/404 ,  G11C11/4091 ,  G11C11/4096

    Abstract: In a memory device, pages are arrayed in a column direction on a substrate, each page constituted by memory cells arrayed in row direction on a substrate. Each memory cell includes a zonal P layer. N+ layers continuous with a source line and a bit line respectively are on both sides of the P layer. Gate insulating layers surround part of the P layer continuous with the N+ layer and part of the P layer continuous with the N+ layer, respectively. One side surface of the gate insulating layer is covered with a gate conductor layer continuous with a first plate line, and the other side surface is covered with a gate conductor layer continuous with a second plate line. A gate conductor layer continuous with a word line surrounds the gate insulating layer.

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