公开(公告)号：US20170179281A1

公开(公告)日：2017-06-22

申请号：US15292778

申请日：2016-10-13

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Clement Merckling ,  Zheng Tao

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/10 ,  H01L21/02 ,  H01L29/20

CPC classification number: H01L29/7827 ,  H01L21/02538 ,  H01L21/02603 ,  H01L29/0676 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/20 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/66666 ,  H01L29/78642

Abstract: A method for forming a semiconductor device is disclosed. The method includes providing a semiconductor substrate. The method also includes epitaxially growing on the semiconductor substrate a first part of a III-V semiconductor nanostructure. The method further includes covering the first part of the III-V semiconductor nanostructure with a layer of a first material. Additionally, the method includes removing a top portion of the layer of the first material. Still further, the method include epitaxially growing on the first part of the III-V semiconductor nanostructure a second part of the III-V semiconductor nanostructure. The method additionally includes covering the second part of the III-V semiconductor nanostructure with a layer of a second material. The second material is different from the first material. Even further, the method includes removing a top portion of the layer of the second material.

公开(公告)号：US20170170346A1

公开(公告)日：2017-06-15

申请号：US15441744

申请日：2017-02-24

Applicant: Advanced Silicon Group, Inc.

Inventor： Marcie R. Black ,  Jeffrey B. Miller ,  Michael Jura ,  Claire Kearns-McCoy ,  Joanne Yim ,  Brian P. Murphy

IPC: H01L31/0352 ,  H01L21/306 ,  H01L29/06 ,  H01L29/16 ,  H01L21/308 ,  H01L21/288 ,  H01L21/3213 ,  H01L31/0224 ,  H01L31/028 ,  H01L31/18 ,  H01L21/285 ,  H01L21/02

CPC classification number: H01L31/035227 ,  B82Y20/00 ,  B82Y30/00 ,  B82Y40/00 ,  H01L21/02068 ,  H01L21/2855 ,  H01L21/28568 ,  H01L21/288 ,  H01L21/30604 ,  H01L21/3081 ,  H01L21/32134 ,  H01L29/0669 ,  H01L29/0676 ,  H01L29/16 ,  H01L31/022408 ,  H01L31/028 ,  H01L31/1804 ,  Y10S977/762 ,  Y10S977/814 ,  Y10S977/834 ,  Y10S977/888 ,  Y10S977/891 ,  Y10S977/892 ,  Y10S977/948

Abstract: In an embodiment of the disclosure, a structure is provided which comprises a silicon substrate and a plurality of necklaces of silicon nanowires which are in direct physical contact with a surface of the silicon substrate, wherein the necklaces cover an area of the silicon substrate.

公开(公告)号：US09679966B2

公开(公告)日：2017-06-13

申请号：US14064858

申请日：2013-10-28

Applicant: Commissariat a L'energie Atomique et aux Energies Alternatives

Inventor： Berangere Hyot ,  Benoit Amstatt ,  Marie-Francoise Armand

IPC: H01L33/12 ,  H01L29/06 ,  H01L21/02 ,  H01L33/04 ,  B82Y10/00 ,  B82Y40/00 ,  C30B25/00 ,  C30B25/18 ,  C30B29/16 ,  C30B29/36 ,  C30B29/40 ,  C30B29/60 ,  H01L29/40 ,  H01L29/66 ,  H01L29/41 ,  H01L33/16 ,  B82Y99/00 ,  H01L33/24

CPC classification number: H01L29/0676 ,  B82Y10/00 ,  B82Y40/00 ,  B82Y99/00 ,  C30B25/005 ,  C30B25/183 ,  C30B29/16 ,  C30B29/36 ,  C30B29/40 ,  C30B29/406 ,  C30B29/605 ,  H01L21/02104 ,  H01L21/02381 ,  H01L21/02389 ,  H01L21/02439 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02603 ,  H01L21/0262 ,  H01L29/401 ,  H01L29/413 ,  H01L29/6609 ,  H01L33/04 ,  H01L33/12 ,  H01L33/16 ,  H01L33/24 ,  Y10S977/762 ,  Y10S977/84 ,  Y10S977/932

Abstract: The electronic device comprises a substrate (1), at least one semiconductor nanowire (2) and a buffer layer (3) interposed between the substrate (1) and said nanowire (2). The buffer layer (3) is at least partly formed by a transition metal nitride layer (9) from which extends the nanowire (2), said transition metal nitride being chosen from: vanadium nitride, chromium nitride, zirconium nitride, niobium nitride, molybdenum nitride, hafnium nitride or tantalum nitride.

公开(公告)号：US20170162250A1

公开(公告)日：2017-06-08

申请号：US15367629

申请日：2016-12-02

Applicant: NaMLab gGmbH

Inventor： Stefan SLESAZECK ,  Halid MULAOSMANOVIC

IPC: G11C11/22 ,  H01L29/78 ,  H01L29/51 ,  H01L27/115 ,  H01L49/02

CPC classification number: G11C11/2275 ,  G11C11/221 ,  G11C11/223 ,  G11C11/2273 ,  G11C11/5657 ,  H01L27/11507 ,  H01L27/1159 ,  H01L28/40 ,  H01L28/60 ,  H01L29/0676 ,  H01L29/516 ,  H01L29/517 ,  H01L29/78391

Abstract: An integrated circuit includes a ferroelectric memory cell. The ferroelectric memory cell includes a ferroelectric layer stack comprising at least one ferroelectric material oxide layer. Each of the ferroelectric material oxide layers includes a ferroelectric material that is at least partially in a ferroelectric state. The ferroelectric layer stack comprises at least two ferroelectric domains. Further, the voltage which is to applied to the layer stack to induce polarization reversal differs for the individual domains such that polarization reversal of individual domains or of a portion of the totality of ferroelectric domains within the ferroelectric material of can be attained.

公开(公告)号：US09673209B2

公开(公告)日：2017-06-06

申请号：US14279842

申请日：2014-05-16

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jean-Pierre Colinge ,  Ta-Pen Guo ,  Carlos H. Diaz

IPC: H01L27/115 ,  H01L27/11556 ,  H01L27/11521 ,  H01L29/788 ,  H01L29/66 ,  H01L29/775 ,  H01L29/792 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11582 ,  H01L21/28 ,  B82Y10/00 ,  H01L29/40 ,  H01L29/423 ,  H01L29/06

CPC classification number: H01L29/7889 ,  B82Y10/00 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11582 ,  H01L29/0676 ,  H01L29/401 ,  H01L29/42324 ,  H01L29/42376 ,  H01L29/66439 ,  H01L29/66666 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/775 ,  H01L29/7883 ,  H01L29/7926

Abstract: A device comprises a nanowire over a substrate, wherein the nanowire comprises a first drain/source region over the substrate, a channel region over the first drain/source region and a second drain/source region over the channel region, a high-k dielectric layer and a control gate layer surrounding a lower portion of the channel region and a tunneling layer and a ring-shaped floating gate layer surrounding an upper portion of the channel region.

公开(公告)号：US09666701B2

公开(公告)日：2017-05-30

申请号：US15074165

申请日：2016-03-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Alan B. Botula ,  Max L. Lifson ,  James A. Slinkman ,  Theodore G. Van Kessel ,  Randy L. Wolf

IPC: H01L29/08 ,  H01L29/732 ,  H01L23/367 ,  H01L23/373 ,  H01L29/78 ,  H01L29/45 ,  H01L23/525 ,  H01L21/02 ,  H01L21/285 ,  H01L21/762 ,  H01L49/02 ,  H01L29/06 ,  H01L29/10 ,  B82Y10/00 ,  H01L29/417 ,  H01L29/41 ,  H01L21/48 ,  H01L23/48 ,  H01L23/485

CPC classification number: H01L23/3677 ,  B82Y10/00 ,  H01L21/02112 ,  H01L21/02178 ,  H01L21/02189 ,  H01L21/02271 ,  H01L21/02488 ,  H01L21/02554 ,  H01L21/02603 ,  H01L21/02628 ,  H01L21/28518 ,  H01L21/2855 ,  H01L21/28568 ,  H01L21/2885 ,  H01L21/32051 ,  H01L21/32053 ,  H01L21/4882 ,  H01L21/7624 ,  H01L23/3731 ,  H01L23/3738 ,  H01L23/481 ,  H01L23/485 ,  H01L23/5256 ,  H01L28/20 ,  H01L29/0649 ,  H01L29/0676 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/413 ,  H01L29/41725 ,  H01L29/45 ,  H01L29/456 ,  H01L29/732 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An approach for heat dissipation in integrated circuit devices is provided. A method includes forming an isolation layer on an electrically conductive feature of an integrated circuit device. The method also includes forming an electrically conductive layer on the isolation layer. The method additionally includes forming a plurality of nanowire structures on a surface of the electrically conductive layer.

公开(公告)号：US09666687B1

公开(公告)日：2017-05-30

申请号：US15187795

申请日：2016-06-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hao-Ming Lee ,  Sheng-Hao Lin ,  Huai-Tzu Chiang

IPC: H01L21/336 ,  H01L29/66 ,  H01L29/06 ,  H01L21/311

CPC classification number: H01L29/66666 ,  H01L21/3086 ,  H01L21/31111 ,  H01L21/31144 ,  H01L29/0649 ,  H01L29/0676 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/7827

Abstract: The present invention provides a method for forming a semiconductor structure, at least including the following steps: first, four sacrificial patterns are formed on a substrate, and a plurality of spacers are then formed surrounding each sacrificial pattern. Next, the four sacrificial patterns are removed, and a photoresist layer is formed between each spacer, covering parts of each spacer. Afterwards, a first etching process is performed to partially remove each spacer, and the photoresist layer is then removed, and a second etching process is then performed, to remove each spacer again, and to form four nanowire hard masks.

公开(公告)号：US20170133513A1

公开(公告)日：2017-05-11

申请号：US15195886

申请日：2016-06-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joon Goo Hong ,  Borna Obradovic ,  Mark Rodder

IPC: H01L29/786 ,  H01L21/225 ,  H01L29/66 ,  H01L29/423 ,  H01L29/06

CPC classification number: H01L29/78642 ,  H01L21/2256 ,  H01L29/0676 ,  H01L29/42392 ,  H01L29/66666 ,  H01L29/66742 ,  H01L29/66772 ,  H01L29/78618 ,  H01L29/78654 ,  H01L29/78684 ,  H01L29/78696

Abstract: A method for making a self-aligned vertical nanosheet field effect transistor. A vertical trench is etched in a layered structure including a plurality of layers, using reactive ion etching, and filled, using an epitaxial process, with a vertical semiconductor nanosheet. A sacrificial layer from among the plurality of layers is etched out and replaced with a conductive (e.g., metal) gate layer coated with a high-dielectric-constant dielectric material. Two other layers from among the plurality of layers, one above and one below the gate layer, are doped, and act as dopant donors for a diffusion process that forms two PN junctions in the vertical semiconductor nanosheet.

公开(公告)号：US09640645B2

公开(公告)日：2017-05-02

申请号：US14018737

申请日：2013-09-05

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Jean-Pierre Colinge ,  Kuo-Cheng Ching ,  Ta-Pen Guo ,  Carlos H. Diaz

IPC: H01L29/775 ,  H01L29/786 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/66 ,  H01L29/06 ,  H01L29/41 ,  H01L29/16

CPC classification number: H01L29/41741 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/28518 ,  H01L29/0676 ,  H01L29/16 ,  H01L29/413 ,  H01L29/66439 ,  H01L29/6653 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/78642

Abstract: A semiconductor device includes a first type region including a first conductivity type. The semiconductor device includes a second type region including a second conductivity type. The semiconductor device includes a channel region extending between the first type region and the second type region. The semiconductor device includes a first silicide region on a first type surface region of the first type region. The first silicide region is separated at least one of a first distance from a first type diffusion region of the first type region or a second distance from the channel region.

公开(公告)号：US20170117206A1

公开(公告)日：2017-04-27

申请号：US15401660

申请日：2017-01-09

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Alan B. BOTULA ,  Max L. LIFSON ,  James A. SLINKMAN ,  Theodore G. VAN KESSEL ,  Randy L. WOLF

IPC: H01L23/367 ,  H01L21/48 ,  H01L29/41 ,  H01L21/3205 ,  H01L21/02 ,  H01L23/373 ,  H01L21/288

CPC classification number: H01L23/3677 ,  B82Y10/00 ,  H01L21/02112 ,  H01L21/02178 ,  H01L21/02189 ,  H01L21/02271 ,  H01L21/02488 ,  H01L21/02554 ,  H01L21/02603 ,  H01L21/02628 ,  H01L21/28518 ,  H01L21/2855 ,  H01L21/28568 ,  H01L21/2885 ,  H01L21/32051 ,  H01L21/32053 ,  H01L21/4882 ,  H01L21/7624 ,  H01L23/3731 ,  H01L23/3738 ,  H01L23/481 ,  H01L23/485 ,  H01L23/5256 ,  H01L28/20 ,  H01L29/0649 ,  H01L29/0676 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/413 ,  H01L29/41725 ,  H01L29/45 ,  H01L29/456 ,  H01L29/732 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An approach for heat dissipation in integrated circuit devices is provided. A method includes forming an isolation layer on an electrically conductive feature of an integrated circuit device. The method also includes forming an electrically conductive layer on the isolation layer. The method additionally includes forming a plurality of nanowire structures on a surface of the electrically conductive layer.