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公开(公告)号：US20240312862A1
公开(公告)日：2024-09-19
申请号：US18674006
申请日：2024-05-24
IPC分类号： H01L23/367 , H01L21/3205 , H01L21/324 , H01L21/74 , H01L21/768 , H01L23/373 , H01L23/48 , H01L23/522 , H01L23/528 , H01L23/532 , H01L27/02
CPC分类号： H01L23/367 , H01L21/32051 , H01L21/32055 , H01L21/324 , H01L21/76895 , H01L23/3735 , H01L23/481 , H01L23/5226 , H01L23/528 , H01L23/53276 , H01L27/0248 , H01L21/743 , H01L23/3677 , H01L2224/48463
摘要： An integrated circuit includes a semiconductor substrate. The integrated circuit also includes a trench in the semiconductor substrate, the trench including a layer of a nanoparticle material. The integrated circuit further includes an interconnect region above the trench.
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公开(公告)号：US20240312838A1
公开(公告)日：2024-09-19
申请号：US18672083
申请日：2024-05-23
发明人： Sheng-Hsiung Wang , Tung-Heng Hsieh , Bao-Ru Young
IPC分类号： H01L21/768 , G06F30/39 , G06F30/398 , G06F119/18 , H01L21/66 , H01L23/50 , H01L23/522 , H01L23/528 , H01L27/02 , H01L27/118
CPC分类号： H01L21/76892 , G06F30/39 , G06F30/398 , H01L21/76895 , H01L22/20 , H01L23/50 , H01L23/5226 , H01L23/5283 , H01L23/5286 , H01L27/0207 , G06F2119/18 , H01L2027/11881
摘要： The present disclosure provides a method for fabricating an integrated circuit (IC). The method includes receiving an IC layout having a first pattern layer that includes first source/drain (S/D) contacts and second S/D contacts, the first and second S/D contacts are spaced away from each other by a spacing along a first direction, and each of the first and second S/D contacts have elongated shapes extending lengthwise in a second direction perpendicular to the first direction. The method includes constructing a conductive feature on a second pattern layer of the IC layout, the conductive feature having an initial rectangular shape with a length and a width, the length extending along the first direction. And the method includes modifying the conductive feature to form a modified conductive feature that is overlapped with the first S/D contacts and distanced away from the second S/D contacts.
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公开(公告)号：USRE50137E1
公开(公告)日：2024-09-17
申请号：US17586023
申请日：2022-01-27
发明人： Jang-Gn Yun , Zhiliang Xia , Ahn-Sik Moon , Se-Jun Park , Joon-Sung Lim , Sung-Min Hwang
IPC分类号： H01L27/1157 , H01L23/522 , H01L23/528 , H01L27/11565 , H01L27/11582 , H10B43/10 , H10B43/27 , H10B43/35
CPC分类号： H10B43/35 , H01L23/5226 , H01L23/528 , H10B43/10 , H10B43/27
摘要： A vertical memory device includes a channel, a dummy channel, a plurality of gate electrodes, and a support pattern. The channel extends in a first direction perpendicular to an upper surface of a substrate. The dummy channel extends from the upper surface of the substrate in the first direction. The plurality of gate electrodes are formed at a plurality of levels, respectively, spaced apart from each other in the first direction on the substrate. Each of the gate electrodes surrounds outer sidewalls of the channel and the dummy channel. The support pattern is between the upper surface of the substrate and a first gate electrode among the gate electrodes. The first gate electrode is at a lowermost one of the levels. The channel and the dummy channel contact each other between the upper surface of the substrate and the first gate electrode.
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公开(公告)号：US12096629B2
公开(公告)日：2024-09-17
申请号：US18344161
申请日：2023-06-29
发明人： Hung-Ling Shih , Yong-Shiuan Tsair
IPC分类号： H01L29/423 , G11C29/14 , H01L21/28 , H01L21/311 , H01L21/3213 , H01L23/522 , H01L23/528 , H01L29/08 , H01L29/66 , H01L29/788 , H10B41/30 , H10B41/42
CPC分类号： H10B41/42 , G11C29/14 , H01L21/31116 , H01L21/32137 , H01L23/5226 , H01L23/528 , H01L29/0847 , H01L29/40114 , H01L29/42328 , H01L29/66825 , H01L29/788 , H10B41/30 , H01L29/66545
摘要： Various embodiments of the present application are directed to a method for forming an integrated circuit (IC) comprising forming a multilayer film to form a plurality of memory cell structures disposed over a substrate and a plurality of memory test structures next to the memory cell structures. A memory test structure comprises a dummy control gate separated from the substrate by a dummy floating gate. The method further comprises forming a conductive floating gate test contact via along sidewalls of the dummy control gate and the dummy floating gate.
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55.发明授权公开(公告)号：US12094842B2
公开(公告)日：2024-09-17
申请号：US16360387
申请日：2019-03-21
发明人： Thorsten Meyer , Walter Hartner , Maciej Wojnowski
CPC分类号： H01L23/66 , H01L23/3114 , H01L23/5226 , H01L23/5227 , H01L24/19 , H01L24/20 , H01L29/0657 , H01Q1/2283 , H01L23/3128 , H01L24/13 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/81 , H01L24/83 , H01L2223/6677 , H01L2224/12105 , H01L2224/13024 , H01L2224/16227 , H01L2224/32225 , H01L2224/73204 , H01L2224/73267 , H01L2224/81203 , H01L2224/81815 , H01L2224/83102 , H01L2224/83825 , H01L2224/8384 , H01L2224/8385 , H01L2924/10158 , H01L2924/15311 , H01L2924/18162 , H01L2224/81815 , H01L2924/00014 , H01L2224/81203 , H01L2924/00014 , H01L2224/8385 , H01L2924/00014 , H01L2224/8384 , H01L2924/00014 , H01L2224/83825 , H01L2924/00014 , H01L2224/83102 , H01L2924/00014
摘要： A semiconductor device includes a semiconductor die having an active main surface and an opposite main surface opposite the active main surface. The semiconductor device further includes an antenna arranged on the active main surface of the semiconductor die and a recess arranged on the opposite main surface of the semiconductor die. The recess is arranged over the antenna.
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公开(公告)号：US12094815B2
公开(公告)日：2024-09-17
申请号：US17460824
申请日：2021-08-30
IPC分类号： H01L23/522 , H01L21/768
CPC分类号： H01L23/5226 , H01L21/76831 , H01L21/76843
摘要： A semiconductor structure includes a substrate with a conductive structure thereon, a first dielectric layer, a conductive feature and a second dielectric layer. The substrate includes a conductive feature. The conductive feature is formed in the first dielectric layer, is electrically connected to the conductive feature. The second dielectric layer is formed on the first dielectric layer and is disposed adjacent to the conductive feature. The first dielectric layer and the second dielectric layer are made of different materials.
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公开(公告)号：US12094770B2
公开(公告)日：2024-09-17
申请号：US17446398
申请日：2021-08-30
发明人： Yao-Min Liu , Ming-Yuan Gao , Ming-Chou Chiang , Shu-Cheng Chin , Huei-Wen Hsieh , Kai-Shiang Kuo , Yen-Chun Lin , Cheng-Hui Weng , Chun-Chieh Lin , Hung-Wen Su
IPC分类号： H01L21/768 , H01L21/304 , H01L23/522 , H01L23/532
CPC分类号： H01L21/76841 , H01L21/304 , H01L21/76802 , H01L21/76877 , H01L23/5226 , H01L23/53238
摘要： In some implementations, one or more semiconductor processing tools may form a via within a substrate of a semiconductor device. The one or more semiconductor processing tools may deposit a ruthenium-based liner within the via. The one or more semiconductor processing tools may deposit, after depositing the ruthenium-based liner, a copper plug within the via.
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公开(公告)号：US12093627B2
公开(公告)日：2024-09-17
申请号：US18053602
申请日：2022-11-08
发明人： Chung-Hui Chen , Tzu Ching Chang , Wan-Te Chen
IPC分类号： G06F30/392 , G03F1/70 , G06F30/3953 , G06F30/398 , H01L23/522
CPC分类号： G06F30/392 , G03F1/70 , G06F30/3953 , G06F30/398 , H01L23/5226
摘要： A method (of forming a semiconductor device) includes: forming an active area structure extending in a first direction; forming gate structures over the active area structure and extending in a second direction substantially perpendicular to the first direction; forming contact-source/drain (CSD) conductors over the active area structure, interleaved with corresponding ones of the gate structures, and extending in the second direction; and forming first conductive segments in a first layer of metallization (M_1st layer) over the active area structure and extending in the first direction, the first conductive segments including a first gate-signal-carrying (GSC) conductor which overlaps the active area structure.
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公开(公告)号：US20240304571A1
公开(公告)日：2024-09-12
申请号：US18663878
申请日：2024-05-14
发明人： Mingni Chang , Yun-Chin Tsou , Ching-Jing Wu , Shiou-Fan Chen , Ming-Yih Wang
IPC分类号： H01L23/58 , H01L21/768 , H01L23/48 , H01L23/522 , H01L25/065
CPC分类号： H01L23/585 , H01L21/76802 , H01L21/76877 , H01L21/76898 , H01L23/481 , H01L25/0657 , H01L23/5226 , H01L2225/06544
摘要： A method includes forming a plurality of low-k dielectric layers over a semiconductor substrate, forming a first plurality of dummy stacked structures extending into at least one of the plurality of low-k dielectric layers, forming a plurality of non-low-k dielectric layers over the plurality of low-k dielectric layers, and forming a second plurality of dummy stacked structures extending into the plurality of non-low-k dielectric layers. The second plurality of dummy stacked structures are over and connected to corresponding ones of the first plurality of dummy stacked structures. The method further includes etching the plurality of non-low-k dielectric layers, the plurality of low-k dielectric layers, and the semiconductor substrate to form a via opening. The via opening is encircled by the first plurality of dummy stacked structures and the second plurality of dummy stacked structures. The via opening is then filled to form a through-via.
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公开(公告)号：US20240304543A1
公开(公告)日：2024-09-12
申请号：US18668038
申请日：2024-05-17
申请人： Intel Corporation
发明人： Kevin Lin , Noriyuki Sato , Tristan Tronic , Michael Christenson , Christopher Jezewski , Jiun-Ruey Chen , James M. Blackwell , Matthew Metz , Miriam Reshotko , Nafees Kabir , Jeffery Bielefeld , Manish Chandhok , Hui Jae Yoo , Elijah Karpov , Carl Naylor , Ramanan Chebiam
IPC分类号： H01L23/522 , H01L21/3213 , H01L21/768 , H01L23/528 , H01L23/532
CPC分类号： H01L23/5226 , H01L21/32139 , H01L21/76819 , H01L21/7682 , H01L21/76843 , H01L23/5283 , H01L23/53209
摘要： IC interconnect structures including subtractively patterned features. Feature ends may be defined through multiple patterning of multiple cap materials for reduced misregistration. Subtractively patterned features may be lines integrated with damascene vias or with subtractively patterned vias, or may be vias integrated with damascene lines or with subtractively patterned lines. Subtractively patterned vias may be deposited as part of a planar metal layer and defined currently with interconnect lines. Subtractively patterned features may be integrated with air gap isolation structures. Subtractively patterned features may be include a barrier material on the bottom, top, or sidewall. A bottom barrier of a subtractively patterned features may be deposited with an area selective technique to be absent from an underlying interconnect feature. A barrier of a subtractively patterned feature may comprise graphene or a chalcogenide of a metal in the feature or in a seed layer.
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