公开(公告)号：US11901289B2

公开(公告)日：2024-02-13

申请号：US17848146

申请日：2022-06-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Wan-Te Chen ,  Chung-Hui Chen ,  Wei-Chih Chen ,  Chii-Ping Chen ,  Wen-Sheh Huang ,  Bi-Ling Lin ,  Sheng-Feng Liu

IPC: H01L23/522 ,  H01L27/06 ,  H01L23/367 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L23/5228 ,  H01L23/3677 ,  H01L27/0629 ,  H01L29/42376 ,  H01L29/78

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a resistive element over the substrate. The semiconductor device structure also includes a thermal conductive element over the substrate. A direct projection of the thermal conductive element on a main surface of the resistive element extends across a portion of a first imaginary line and a portion of a second imaginary line of the main surface. The first imaginary line is perpendicular to the second imaginary line, and the first imaginary line and the second imaginary line intersect at a center of the main surface.

公开(公告)号：US12094872B2

公开(公告)日：2024-09-17

申请号：US17643651

申请日：2021-12-10

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chung-Hui Chen ,  Wan-Te Chen ,  Shu-Wei Chung ,  Tung-Heng Hsieh ,  Tzu-Ching Chang ,  Tsung-Hsin Yu ,  Yung Feng Chang

IPC: H01L27/06 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L27/0629 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/78696

Abstract: A semiconductor device includes a substrate. A first nanosheet structure and a second nanosheet structure are disposed on the substrate. Each of the first and second nanosheet structures have at least one nanosheet forming source/drain regions and a gate structure including a conductive gate contact. A first oxide structure is disposed on the substrate between the first and second nanosheet structures. A conductive terminal is disposed in or on the first oxide structure. The conductive terminal, the first oxide structure and the gate structure of the first nanosheet structure define a capacitor.

公开(公告)号：US11670501B2

公开(公告)日：2023-06-06

申请号：US17219173

申请日：2021-03-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Hsiu-Wen Hsueh ,  Yu-Hsiang Chen ,  Wen-Sheh Huang ,  Chii-Ping Chen ,  Wan-Te Chen

IPC: H01L21/02 ,  H01L21/762 ,  H01L27/06 ,  H01L23/64 ,  H01L21/304 ,  H01L27/08 ,  H01L23/522 ,  H01L49/02 ,  H01L23/528 ,  H01L23/34

CPC classification number: H01L21/022 ,  H01L21/304 ,  H01L21/762 ,  H01L23/5228 ,  H01L23/647 ,  H01L27/0635 ,  H01L27/0802 ,  H01L28/24 ,  H01L23/345 ,  H01L23/528 ,  H01L23/5226 ,  H01L28/20

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate, a first resistive element and a second resistive element over the semiconductor substrate. A topmost surface of the second resistive element is higher than a topmost surface of the first resistive element. The semiconductor device structure also includes a first conductive feature and a second conductive feature electrically connected to the first resistive element. The second resistive element is between and electrically isolated from the first conductive feature and the second conductive feature. The semiconductor device structure further includes a first dielectric layer surrounding the first conductive feature and the second conductive feature.

公开(公告)号：US11494542B2

公开(公告)日：2022-11-08

申请号：US16741440

申请日：2020-01-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Chung-Hui Chen ,  Tzu Ching Chang ,  Wan-Te Chen

IPC: G06F30/392 ,  H01L23/522 ,  G03F1/70 ,  G06F30/3953 ,  G06F30/398

Abstract: A semiconductor device includes: an active area in a transistor layer; contact-source/drain (CSD) conductors in the transistor layer; gate conductors in the transistor layer, and interleaved with the CSD conductors; VG structures in the transistor layer, and over the active area; and a first gate-signal-carrying (GSC) conductor in an M_1st layer that is over the transistor layer, and that is over the active area; and wherein long axes correspondingly of the active area and the first GSC conductor extend substantially in a first direction; and long axes correspondingly of the CSD conductors and the gate conductors extend substantially in a second direction, the second direction being substantially perpendicular to the first direction.

公开(公告)号：US20220278099A1

公开(公告)日：2022-09-01

申请号：US17542014

申请日：2021-12-03

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chung-Hui Chen ,  Tzu-Ching Chang ,  Weichih Chen ,  Wan-Te Chen ,  Tsung-Hsin Yu ,  Cheng-Hsiang Hsieh

IPC: H01L27/092 ,  G06F30/392 ,  G06F30/36 ,  G06F30/327

Abstract: An integrated circuit (IC) including a plurality of finfet cells designed with digital circuit design rules to provide smaller finfet cells with decreased cell heights, and analog circuit cell structures including first finfet cells of the plurality of finfet cells and including at least one cut metal layer. The smaller finfet cells with decreased cell heights provide a first shorter metal track in one direction and the at least one cut metal layer provides a second shorter metal track in another direction to increase maximum electromigration currents in the integrated circuit.

公开(公告)号：US09343552B2

公开(公告)日：2016-05-17

申请号：US14719090

申请日：2015-05-21

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Wan-Te Chen ,  Chung-Hui Chen ,  Jaw-Juinn Horng ,  Po-Zeng Kang

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/93 ,  H01L29/66 ,  H01L27/02 ,  H01L27/06 ,  H01L27/092 ,  H01L27/12 ,  H01L21/8234

CPC classification number: H01L29/6681 ,  H01L21/823418 ,  H01L21/823431 ,  H01L27/0207 ,  H01L27/0629 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/66174 ,  H01L29/7851

Abstract: Embodiments of the present disclosure are a semiconductor device, a FinFET device, and a method of forming a FinFET device. An embodiment is semiconductor device including a first FinFET over a substrate, wherein the first FinFET includes a first set of semiconductor fins. The semiconductor device further includes a first body contact for the first FinFET over the substrate, wherein the first body contact includes a second set of semiconductor fins, and wherein the first body contact is laterally adjacent the first FinFET.

公开(公告)号：US09064725B2

公开(公告)日：2015-06-23

申请号：US13715684

申请日：2012-12-14

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Wan-Te Chen ,  Chung-Hui Chen ,  Jaw-Juinn Horng ,  Po-Zeng Kang

IPC: H01L29/78 ,  H01L27/088 ,  H01L27/02 ,  H01L27/092 ,  H01L27/12 ,  H01L29/66 ,  H01L27/06

CPC classification number: H01L29/6681 ,  H01L21/823418 ,  H01L21/823431 ,  H01L27/0207 ,  H01L27/0629 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/66174 ,  H01L29/7851

Abstract: Embodiments of the present disclosure are a semiconductor device, a FinFET device, and a method of forming a FinFET device. An embodiment is semiconductor device including a first FinFET over a substrate, wherein the first FinFET includes a first set of semiconductor fins. The semiconductor device further includes a first body contact for the first FinFET over the substrate, wherein the first body contact includes a second set of semiconductor fins, and wherein the first body contact is laterally adjacent the first FinFET.

Abstract translation: 本公开的实施例是半导体器件，FinFET器件和形成FinFET器件的方法。 一个实施例是在衬底上包括第一FinFET的半导体器件，其中第一FinFET包括第一组半导体鳍片。 半导体器件还包括用于衬底上的第一FinFET的第一体接触，其中第一体接触包括第二组半导体鳍片，并且其中第一体接触件与第一FinFET横向相邻。

公开(公告)号：US20140167172A1

公开(公告)日：2014-06-19

申请号：US13715684

申请日：2012-12-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Wan-Te Chen ,  Chung-Hui Chen ,  Jaw-Juinn Horng ,  Po-Zeng Kang

IPC: H01L27/04 ,  H01L21/77 ,  H01L27/088

CPC classification number: H01L29/6681 ,  H01L21/823418 ,  H01L21/823431 ,  H01L27/0207 ,  H01L27/0629 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/66174 ,  H01L29/7851

Abstract: Embodiments of the present disclosure are a semiconductor device, a FinFET device, and a method of forming a FinFET device. An embodiment is semiconductor device including a first FinFET over a substrate, wherein the first FinFET includes a first set of semiconductor fins. The semiconductor device further includes a first body contact for the first FinFET over the substrate, wherein the first body contact includes a second set of semiconductor fins, and wherein the first body contact is laterally adjacent the first FinFET.

Abstract translation: 本公开的实施例是半导体器件，FinFET器件和形成FinFET器件的方法。 一个实施例是在衬底上包括第一FinFET的半导体器件，其中第一FinFET包括第一组半导体鳍片。 半导体器件还包括用于衬底上的第一FinFET的第一体接触，其中第一体接触包括第二组半导体鳍片，并且其中第一体接触件与第一FinFET横向相邻。

公开(公告)号：US20240387518A1

公开(公告)日：2024-11-21

申请号：US18787569

申请日：2024-07-29

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chung-Hui Chen ,  Wan-Te Chen ,  Shu-Wei Chung ,  Tung-Heng Hsieh ,  Tzu-Ching Chang ,  Tsung-Hsin Yu ,  Yung Feng Chang

IPC: H01L27/06 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

Abstract: A semiconductor device includes a substrate. A first nanosheet structure and a second nanosheet structure are disposed on the substrate. Each of the first and second nanosheet structures have at least one nanosheet forming source/drain regions and a gate structure including a conductive gate contact. A first oxide structure is disposed on the substrate between the first and second nanosheet structures. A conductive terminal is disposed in or on the first oxide structure. The conductive terminal, the first oxide structure and the gate structure of the first nanosheet structure define a capacitor.

公开(公告)号：US11901283B2

公开(公告)日：2024-02-13

申请号：US17371641

申请日：2021-07-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Wan-Te Chen ,  Chung-Hui Chen ,  Wei Chih Chen

IPC: H01L23/522 ,  H01L21/768 ,  H01L49/02

CPC classification number: H01L23/5223 ,  H01L21/76805 ,  H01L23/5226 ,  H01L28/91

Abstract: An integrated circuit (IC) structure includes a semiconductor substrate, a bottom electrode routing, a capacitor structure, a top electrode routing. The bottom electrode routing is over the semiconductor substrate. The capacitor structure is over the bottom electrode routing. The capacitor structure includes a bottom metal layer, a middle metal layer above the bottom metal layer, and a top metal layer above the middle metal layer. When viewed in a plan view, the top metal layer has opposite straight edges extending along a first direction and opposite square wave-shaped edges connecting the opposite straight edges, the square wave-shaped edges each comprise alternating first and second segments extending along a second direction perpendicular to the first direction, and third segments each connecting adjacent two of the first and second segments, wherein the third segments extend along the first direction.