公开(公告)号：US12165972B2

公开(公告)日：2024-12-10

申请号：US17412872

申请日：2021-08-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chung-Hui Chen

IPC: H01L23/528 ,  G06F30/00 ,  G06F30/394 ,  H01L21/033 ,  H01L21/311 ,  H01L21/768 ,  H01L27/02 ,  H01L27/118

Abstract: A method includes identifying at least a first mask or a second mask, fabricating, by the first mask, a first conductive line, fabricating, by the second mask, a second conductive line, and fabricating, by the first mask, a third conductive line if a dimension of the first conductive line is larger than a corresponding dimension of the second conductive line, or fabricating, by the second mask, the third conductive line if the dimension of the first conductive line is less than the corresponding dimension of the second conductive line A first circuit element is coupled to a second circuit element by at least the third conductive line, and the first circuit element is separated from the second circuit element by a predetermined distance.

公开(公告)号：US11967621B2

公开(公告)日：2024-04-23

申请号：US18155887

申请日：2023-01-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chung-Hui Chen ,  Tung-Tsun Chen ,  Jui-Cheng Huang

IPC: H01L29/417 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/40 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786 ,  H01L23/34 ,  H01L27/06

CPC classification number: H01L29/4175 ,  H01L21/823418 ,  H01L21/823475 ,  H01L21/823814 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/41725 ,  H01L29/41766 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/7845 ,  H01L29/78618 ,  H01L23/345 ,  H01L27/0629

Abstract: A method of manufacturing a semiconductor structure includes forming an active region having a first portion which is doped. The method further includes forming a first silicide layer over and electrically coupled to the first portion of the active region. The method further includes forming a second silicide layer under and electrically coupled to the first portion of the active region. The method further includes forming a first metal-to-drain/source (MD) contact structure over and electrically coupled to the first silicide layer. The method further includes forming a first via-to-MD (VD) structure over and electrically coupled to the MD contact structure. The method further includes forming a buried via-to-source/drain (BVD) structure under and electrically coupled to the second silicide layer.

公开(公告)号：US11901289B2

公开(公告)日：2024-02-13

申请号：US17848146

申请日：2022-06-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Wan-Te Chen ,  Chung-Hui Chen ,  Wei-Chih Chen ,  Chii-Ping Chen ,  Wen-Sheh Huang ,  Bi-Ling Lin ,  Sheng-Feng Liu

IPC: H01L23/522 ,  H01L27/06 ,  H01L23/367 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L23/5228 ,  H01L23/3677 ,  H01L27/0629 ,  H01L29/42376 ,  H01L29/78

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a resistive element over the substrate. The semiconductor device structure also includes a thermal conductive element over the substrate. A direct projection of the thermal conductive element on a main surface of the resistive element extends across a portion of a first imaginary line and a portion of a second imaginary line of the main surface. The first imaginary line is perpendicular to the second imaginary line, and the first imaginary line and the second imaginary line intersect at a center of the main surface.

公开(公告)号：US11563095B2

公开(公告)日：2023-01-24

申请号：US17175064

申请日：2021-02-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chung-Hui Chen ,  Tung-Tsun Chen ,  Jui-Cheng Huang

IPC: H01L29/417 ,  H01L29/08 ,  H01L29/40 ,  H01L29/786 ,  H01L29/49 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/66 ,  H01L27/06 ,  H01L23/34

Abstract: A semiconductor device including: a first S/D arrangement including a silicide-sandwiched portion of a corresponding active region having a silicide-sandwiched configuration, a first portion of a corresponding metal-to-drain/source (MD) contact structure, a first via-to-MD (VD) structure, and a first buried via-to-source/drain (BVD) structure; a gate structure over a channel portion of the corresponding active region; and a second S/D arrangement including a first doped portion of the corresponding active region; and at least one of the following: an upper contact arrangement including a first silicide layer over the first doped portion, a second portion of the corresponding MD contact structure; and a second VD structure; or a lower contact arrangement including a second silicide layer under the first doped portion, and a second BVD structure.

公开(公告)号：US20220405457A1

公开(公告)日：2022-12-22

申请号：US17476615

申请日：2021-09-16

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shu-Wei Chung ,  Tung-Heng Hsieh ,  Chung-Hui Chen ,  Chung-Yi Lin

IPC: G06F30/392 ,  G06F30/398 ,  G06F30/323

Abstract: An analog standard cell is provided. An analog standard cell according to the present disclosure includes a first active region and a second active region extending along a first direction, and a plurality of conductive lines in a first metal layer over the first active region and the second active region. The plurality of conductive lines includes a first conductive line and a second conductive line disposed directly over the first active region, a third conductive line and a fourth conductive line disposed directly over the second active region, a middle conductive line disposed between the second conductive line and the third conductive line, a first power line spaced apart from the middle conductive line by the first conductive line and the second conductive line, and a second power line spaced apart from the middle conductive line by the third conductive line and the fourth conductive line.

公开(公告)号：US20220278091A1

公开(公告)日：2022-09-01

申请号：US17543255

申请日：2021-12-06

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chung-Hui Chen ,  Weichih Chen ,  Tien-Chien Huang ,  Chien-Chun Tsai ,  Ruey-Bin Sheen ,  Tsung-Hsin Yu ,  Chih-Hsien Chang ,  Cheng-Hsiang Hsieh

IPC: H01L27/02 ,  H01L29/417 ,  H01L29/40 ,  H01L21/8234 ,  H01L27/088 ,  H03K17/687

Abstract: A semiconductor structure including first finfet cells and second finfet cells. Each of the first finfet cells has an analog fin boundary according to analog circuit design rules, and each of the second finfet cells has a digital fin boundary according to digital circuit design rules. The semiconductor structure further includes first circuits formed with the first finfet cells, second circuits formed with the second finfet cells, and third circuits formed with one or more of the first finfet cells and one or more of the second finfet cells.

公开(公告)号：US10396217B2

公开(公告)日：2019-08-27

申请号：US15389173

申请日：2016-12-22

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chung-Hui Chen

IPC: H01L21/762 ,  H01L49/02 ,  H01L29/94 ,  H01L29/66 ,  H01L27/08 ,  H01L27/06 ,  H01L27/088 ,  H01L29/78 ,  H01L27/12

Abstract: A semiconductor device including field-effect transistors (finFETs) and fin capacitors are formed on a silicon substrate. The fin capacitors include silicon fins, one or more electrical conductors between the silicon fins, and insulating material between the silicon fins and the one or more electrical conductors. The fin capacitors may also include insulating material between the one or more electrical conductors and underlying semiconductor material.

公开(公告)号：US10354920B2

公开(公告)日：2019-07-16

申请号：US15231215

申请日：2016-08-08

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Pai-Chieh Wang ,  Tung-Heng Hsieh ,  Yimin Huang ,  Chung-Hui Chen

IPC: H01L27/07 ,  H01L21/822 ,  H01L21/8234 ,  H01L29/94 ,  H01L27/06 ,  H01L27/08 ,  H01L49/02 ,  H01L29/40

Abstract: Methods and apparatus for polysilicon MOS capacitors in a replacement gate process. A method includes disposing a gate dielectric layer over a semiconductor substrate; disposing a polysilicon gate layer over the dielectric layer; patterning the gate dielectric layer and the polysilicon gate layer to form a plurality of polysilicon gates spaced by at least a minimum polysilicon to polysilicon pitch; defining a polysilicon resistor region containing at least one of the polysilicon gates and not containing at least one other of the polysilicon gates, which form dummy gates; depositing a mask layer over an inter-level dielectric layer; patterning the mask layer to expose the dummy gates; removing the dummy gates and the gate dielectric layer underneath the dummy gates to leave trenches in the inter-level dielectric layer; and forming high-k metal gate devices in the trenches in the inter-level dielectric layer. An apparatus produced by the method is disclosed.

公开(公告)号：US09911819B2

公开(公告)日：2018-03-06

申请号：US15479803

申请日：2017-04-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Chung-Hui Chen

IPC: H01L29/06 ,  H01L29/423 ,  H01L27/088 ,  H01L29/78 ,  H01L21/8234

CPC classification number: H01L29/42392 ,  H01L21/823487 ,  H01L27/0207 ,  H01L27/088 ,  H01L29/0676 ,  H01L29/66666 ,  H01L29/7827

Abstract: A semiconductor structure includes a first GAA transistor and a second GAA transistor. The first GAA transistor includes: a first top OD region, a first bottom OD region, and a first nanowire. A second GAA transistor includes: a second top OD region, a second bottom OD region, and a second nanowire. The first top OD region, the first bottom OD region, and the first nanowire are symmetrical with the second top OD region, the second bottom OD region, and the second nanowire respectively, the first GAA transistor is arranged to provide a first current to flow from the first top OD region to the first bottom OD region, and the second GAA transistor is arranged to provide a second current to flow from the second top OD region to the second bottom OD region.

公开(公告)号：US09627479B2

公开(公告)日：2017-04-18

申请号：US15048677

申请日：2016-02-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Chung-Hui Chen

IPC: H01L29/06 ,  H01L27/088 ,  H01L29/78 ,  H01L27/02 ,  H01L29/423 ,  H01L29/66 ,  H01L21/8234

CPC classification number: H01L29/42392 ,  H01L21/823487 ,  H01L27/0207 ,  H01L27/088 ,  H01L29/0676 ,  H01L29/66666 ,  H01L29/7827

Abstract: In some embodiments, a semiconductor structure includes first and second GAA structures configured to form corresponding similar first and second circuits. At least one of the first or second GAA structure includes at least one GAA device. A GAA device of the at least one GAA device includes at least one nanowire and a gate region. A nanowire of the at least one nanowire has a cross-section asymmetrical with respect to a middle line of the cross-section. The cross-section has first and second end lines substantially parallel the middle line. The first end line is shorter than the second end line. The gate region wraps all around part of the nanowire. The first and second GAA structures have substantially a same of a number of GAA devices in the at least one GAA device configured to have current flow from the first end line to the second end line.