公开(公告)号：US20180047692A1

公开(公告)日：2018-02-15

申请号：US15233271

申请日：2016-08-10

Applicant: Amkor Technology, Inc.

Inventor： Glenn Rinne ,  Daniel Richter

IPC: H01L23/00

CPC classification number: H01L24/14 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/06051 ,  H01L2224/06177 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/13012 ,  H01L2224/13014 ,  H01L2224/13015 ,  H01L2224/13016 ,  H01L2224/13017 ,  H01L2224/131 ,  H01L2224/14051 ,  H01L2224/14131 ,  H01L2224/14133 ,  H01L2224/14135 ,  H01L2224/14141 ,  H01L2224/14151 ,  H01L2224/14153 ,  H01L2224/14154 ,  H01L2224/14177 ,  H01L2224/81815 ,  H01L2924/10156 ,  H01L2924/15311 ,  H01L21/78 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/014

Abstract: Provided is a disclosure for optimizing the number of semiconductor devices on a wafer/substrate. The optimization comprises laying out, cutting, and packaging the devices efficiently.

公开(公告)号：US20170338197A1

公开(公告)日：2017-11-23

申请号：US15674406

申请日：2017-08-10

Applicant: Renesas Electronics Corporation

Inventor： Shinya Suzuki

IPC: H01L23/00 ,  G02F1/133 ,  H01L23/528 ,  H01L23/522 ,  H01L23/485 ,  H01L21/768 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/02 ,  G02F1/1345 ,  G02F1/1343 ,  G02F1/1333 ,  H01L27/13 ,  H01L29/78 ,  G02F1/1368 ,  G02F1/1362

CPC classification number: H01L24/14 ,  G02F1/13306 ,  G02F1/133345 ,  G02F1/134309 ,  G02F1/13439 ,  G02F1/1345 ,  G02F1/13458 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/133302 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/768 ,  H01L21/76819 ,  H01L23/485 ,  H01L23/522 ,  H01L23/528 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/81 ,  H01L24/83 ,  H01L27/13 ,  H01L29/7833 ,  H01L2224/02122 ,  H01L2224/0345 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05073 ,  H01L2224/05075 ,  H01L2224/051 ,  H01L2224/05144 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05553 ,  H01L2224/056 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/13005 ,  H01L2224/13006 ,  H01L2224/13009 ,  H01L2224/13013 ,  H01L2224/13022 ,  H01L2224/13027 ,  H01L2224/13144 ,  H01L2224/14153 ,  H01L2224/16225 ,  H01L2224/271 ,  H01L2224/2929 ,  H01L2224/29355 ,  H01L2224/29444 ,  H01L2224/32225 ,  H01L2224/81 ,  H01L2224/81191 ,  H01L2224/8185 ,  H01L2224/83101 ,  H01L2224/83203 ,  H01L2224/83851 ,  H01L2224/9211 ,  H01L2224/93 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01041 ,  H01L2924/01057 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/04941 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1426 ,  H01L2924/15788 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2224/11 ,  H01L2224/83 ,  H01L2924/00

Abstract: A technique which improves the reliability in coupling between a bump electrode of a semiconductor chip and wiring of a mounting substrate, more particularly a technique which guarantees the flatness of a bump electrode even when wiring lies in a top wiring layer under the bump electrode, thereby improving the reliability in coupling between the bump electrode and the wiring formed on a glass substrate. Wiring, comprised of a power line or signal line, and a dummy pattern are formed in a top wiring layer beneath a non-overlap region of a bump electrode. The dummy pattern is located to fill the space between wiring to reduce irregularities caused by the wiring and space in the top wiring layer. A surface protection film formed to cover the top wiring layer is flattened by CMP.

公开(公告)号：US09818678B2

公开(公告)日：2017-11-14

申请号：US14222649

申请日：2014-03-23

Applicant: Renesas Electronics Corporation

Inventor： Jumpei Konno ,  Takafumi Nishita ,  Nobuhiro Kinoshita ,  Kazunori Hasegawa ,  Michiaki Sugiyama

IPC: H01L21/48 ,  H01L23/498 ,  H01L23/00 ,  H01L21/683 ,  H01L21/56

CPC classification number: H01L23/49811 ,  H01L21/4853 ,  H01L21/563 ,  H01L21/6836 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/16 ,  H01L24/45 ,  H01L24/81 ,  H01L24/85 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/05554 ,  H01L2224/10175 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/136 ,  H01L2224/14153 ,  H01L2224/14155 ,  H01L2224/1601 ,  H01L2224/16105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81194 ,  H01L2224/81385 ,  H01L2224/814 ,  H01L2224/81444 ,  H01L2224/83102 ,  H01L2224/85 ,  H01L2224/85203 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/014 ,  H01L2224/11 ,  H01L2924/00 ,  H01L2224/48

Abstract: To improve reliability of a semiconductor device, in a flip-chip bonding step, a solder material that is attached to a tip end surface of a projecting electrode in advance and a solder material that is applied in advance over a terminal (bonding lead) are heated and thereby integrated and electrically connected to each other. The terminal includes a wide part (a first portion) with a first width W1 and a narrow part (a second portion) with a second width W2. When the solder material is heated, the thickness of the solder material arranged over the narrow part becomes smaller than the thickness of the solder material arranged in the wide part. Then, in the flip-chip bonding step, a projecting electrode is arranged over the narrow part and bonded onto the narrow part. Thus, the amount of protrusion of the solder material can be reduced.

公开(公告)号：US20160181223A1

公开(公告)日：2016-06-23

申请号：US15057302

申请日：2016-03-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Horng Chang ,  Tin-Hao Kuo ,  Chen-Shien Chen ,  Yen-Liang Lin

IPC: H01L23/00 ,  H01L25/00

CPC classification number: H01L24/16 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/81 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05552 ,  H01L2224/05572 ,  H01L2224/05599 ,  H01L2224/10145 ,  H01L2224/11849 ,  H01L2224/13011 ,  H01L2224/13012 ,  H01L2224/13015 ,  H01L2224/13018 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/14051 ,  H01L2224/1412 ,  H01L2224/14152 ,  H01L2224/14153 ,  H01L2224/16238 ,  H01L2224/81191 ,  H01L2224/81345 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/2064 ,  Y10T428/12493 ,  Y10T428/24479 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: In some embodiments, the present invention relates to a method of integrated chip bonding. The method forms a conductive trace on a surface of a first work piece, and a conductive bump on a surface of a second work piece. The conductive bump has a recess. A reflow process is performed on a solder layer to electrically couple the conductive trace and the conductive bump. The solder layer fills a part of the recess during the reflow process. By filling the recess during the reflow process, electrical shorting between the conductive trace and an adjacent conductive is reduced.

Abstract translation: 在一些实施例中，本发明涉及集成芯片接合的方法。 该方法在第一工件的表面上形成导电迹线，并在第二工件的表面上形成导电凸块。 导电凸块具有凹部。 在焊料层上进行回流处理，以电耦合导电迹线和导电凸块。 在回流过程中，焊料层填充凹部的一部分。 通过在回流工艺期间填充凹槽，导电迹线和相邻导电体之间的电短路减小。

公开(公告)号：US20160126203A1

公开(公告)日：2016-05-05

申请号：US14993981

申请日：2016-01-12

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shinya Suzuki

IPC: H01L23/00 ,  H01L21/311 ,  H01L21/02 ,  H01L21/768 ,  H01L21/3105

CPC classification number: H01L24/14 ,  G02F1/13306 ,  G02F1/133345 ,  G02F1/134309 ,  G02F1/13439 ,  G02F1/1345 ,  G02F1/13458 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/133302 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/768 ,  H01L21/76819 ,  H01L23/485 ,  H01L23/522 ,  H01L23/528 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/81 ,  H01L24/83 ,  H01L27/13 ,  H01L29/7833 ,  H01L2224/02122 ,  H01L2224/0345 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05073 ,  H01L2224/05075 ,  H01L2224/051 ,  H01L2224/05144 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05553 ,  H01L2224/056 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/13005 ,  H01L2224/13006 ,  H01L2224/13009 ,  H01L2224/13013 ,  H01L2224/13022 ,  H01L2224/13027 ,  H01L2224/13144 ,  H01L2224/14153 ,  H01L2224/16225 ,  H01L2224/271 ,  H01L2224/2929 ,  H01L2224/29355 ,  H01L2224/29444 ,  H01L2224/32225 ,  H01L2224/81 ,  H01L2224/81191 ,  H01L2224/8185 ,  H01L2224/83101 ,  H01L2224/83203 ,  H01L2224/83851 ,  H01L2224/9211 ,  H01L2224/93 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01041 ,  H01L2924/01057 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/04941 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1426 ,  H01L2924/15788 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2224/11 ,  H01L2224/83 ,  H01L2924/00

Abstract: A technique which improves the reliability in coupling between a bump electrode of a semiconductor chip and wiring of a mounting substrate, more particularly a technique which guarantees the flatness of a bump electrode even when wiring lies in a top wiring layer under the bump electrode, thereby improving the reliability in coupling between the bump electrode and the wiring formed on a glass substrate. Wiring, comprised of a power line or signal line, and a dummy pattern are formed in a top wiring layer beneath a non-overlap region of a bump electrode. The dummy pattern is located to fill the space between wirings to reduce irregularities caused by the wirings and space in the top wiring layer. A surface protection film formed to cover the top wiring layer is flattened by CMP.

公开(公告)号：US09318458B2

公开(公告)日：2016-04-19

申请号：US14800934

申请日：2015-07-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chih-Horng Chang ,  Tin-Hao Kuo ,  Chen-Shien Chen ,  Yen-Liang Lin

IPC: H01L23/00

CPC classification number: H01L24/16 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/81 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05552 ,  H01L2224/05572 ,  H01L2224/05599 ,  H01L2224/10145 ,  H01L2224/11849 ,  H01L2224/13011 ,  H01L2224/13012 ,  H01L2224/13015 ,  H01L2224/13018 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/14051 ,  H01L2224/1412 ,  H01L2224/14152 ,  H01L2224/14153 ,  H01L2224/16238 ,  H01L2224/81191 ,  H01L2224/81345 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/2064 ,  Y10T428/12493 ,  Y10T428/24479 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A bump structure includes a first end; and a second end opposite the first end. The bump structure further includes a side connected between the first end and the second end, wherein the side comprises a recess for a reflowed solder material to fill, and the recess defines a first surface adjacent to the first end and a second surface adjacent to the second end.

Abstract translation: 凸块结构包括第一端; 以及与第一端相对的第二端。 凸起结构还包括连接在第一端和第二端之间的侧面，其中侧面包括用于回流焊料材料填充的凹槽，凹部限定与第一端相邻的第一表面和邻近第一端的第二表面 第二端

公开(公告)号：US09288910B2

公开(公告)日：2016-03-15

申请号：US14555856

申请日：2014-11-28

Applicant: IBIDEN CO., LTD.

Inventor： Keisuke Shimizu ,  Yuichi Nakamura ,  Tsuyoshi Yamaguchi

IPC: H05K1/18 ,  H05K3/30 ,  H01L23/13 ,  H01L23/498 ,  H01L23/538 ,  H05K3/46

CPC classification number: H05K1/183 ,  H01L23/13 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L2224/04105 ,  H01L2224/06152 ,  H01L2224/06153 ,  H01L2224/12105 ,  H01L2224/14152 ,  H01L2224/14153 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/15153 ,  H01L2924/15313 ,  H05K1/181 ,  H05K1/185 ,  H05K3/30 ,  H05K3/4602 ,  H05K2201/096 ,  H05K2201/10674 ,  Y10T29/4913

Abstract: A substrate with a built-in electronic component includes multiple resin insulating layers including first, second, third and fourth insulating layers, multiple conductor layers including a first wiring layer including a first pad, a second wiring layer including a second pad, and a third wiring layer including third and fourth pads, multiple via conductors including a first via connecting the first and second pads through the second insulating layer, a second via connecting the second and third pads through the third and fourth insulating layers, and a third via connected to the fourth pad through the fourth insulating layer, and an electronic component positioned a cavity through the second and third insulating layers such that the third via is connecting terminal of the component and fourth pad. The second and third vias have filled plating filling opening portions through the third and fourth insulating layers and through the fourth insulating layer.

Abstract translation: 具有内置电子部件的基板包括包括第一，第二，第三和第四绝缘层的多个树脂绝缘层，多个导体层，包括包括第一焊盘的第一布线层，包括第二焊盘的第二布线层和第三焊盘的第三布线层 包括第三和第四焊盘的布线层，多个通孔导体，包括通过第二绝缘层连接第一和第二焊盘的第一通孔，通过第三和第四绝缘层连接第二和第三焊盘的第二通孔，以及连接到 通过第四绝缘层的第四焊盘和通过第二和第三绝缘层定位空腔的电子部件，使得第三通孔是部件和第四焊盘的连接端子。 第二和第三通孔已经通过第三绝缘层和第四绝缘层填充电镀填充开口部分并穿过第四绝缘层。

公开(公告)号：US09171812B1

公开(公告)日：2015-10-27

申请号：US14088882

申请日：2013-11-25

Applicant: Amkor Technology, Inc.

Inventor： Byong Jin Kim ,  Min Chul Shin ,  Ho Choi

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/00 ,  H01L23/00

CPC classification number: H01L24/06 ,  B23K1/0016 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/10175 ,  H01L2224/13014 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/14153 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81191 ,  H01L2224/81385 ,  H01L2224/814 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/014

Abstract: Methods and devices for a semiconductor device having conductive pads to prevent solder reflow are disclosed and may include a substrate comprising conductive pads of rectangular shape and neck-down portions on opposite sides of the rectangular shape, a semiconductor die comprising conductive pillars, and a solder electrically coupling the conductive pillars to the conductive pads. The neck-down portions may comprise a solder mask for the conductive pads to prevent solder from flowing in an unwanted direction on the conductive pads. The conductive pillars may comprise an elliptical cross-section with a minor axis length X and a major axis length Y. The major axis of the elliptical cross-section may be parallel to a long axis of the rectangular shape of the conductive pads. A decrease (W) in width of the conductive pads from the rectangular shape to the neck-down portions may be defined by X/5≦W≦X/2.

Abstract translation: 公开了具有用于防止焊料回流的导电焊盘的半导体器件的方法和器件，并且可以包括：衬底，其包括矩形形状的导电焊盘和矩形相对侧上的颈缩部分，包括导电柱的半导体管芯和焊料 将导电柱电耦合到导电垫。 颈缩部分可以包括用于导电焊盘的焊接掩模，以防止焊料在导电焊盘上以不期望的方向流动。 导电柱可以包括具有短轴长度X和长轴长度Y的椭圆形横截面。椭圆形截面的长轴可以平行于导电垫的矩形形状的长轴。 导电焊盘从矩形到颈缩部分的宽度的减小（W）可以通过X / 5＆amp; NlE; W＆nlE; X / 2来限定。

公开(公告)号：US20150061723A1

公开(公告)日：2015-03-05

申请号：US14474563

申请日：2014-09-02

Applicant: Japan Display Inc.

Inventor： Chunhan ZHANG ,  Yoshihiro KOTANI

IPC: H01L23/498 ,  G09G3/00 ,  H01L27/12

CPC classification number: G09G3/006 ,  G02F1/13454 ,  G02F1/13458 ,  G02F2203/69 ,  H01L22/34 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/13013 ,  H01L2224/14153 ,  H01L2224/14155 ,  H01L2224/16227 ,  H01L2224/27334 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32225 ,  H01L2224/81191 ,  H01L2224/81903 ,  H01L2224/83192 ,  H01L2224/83203 ,  H01L2224/83851 ,  H01L2224/9212 ,  H01L2924/15788 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00014 ,  H01L2924/07811

Abstract: A display device includes, on a TFT substrate, a driver IC having a first bump and a second bump, a first terminal and a second terminal connecting respectively to the first bump and the second bump, and wiring interconnecting the first terminal and the second terminal. The driver IC also includes a resistance detection circuit that detects resistance between the first bump and the second bump.

Abstract translation: 一种显示装置，在TFT基板上具有具有第一凸块和第二凸块的驱动器IC，分别连接到第一凸块和第二凸块的第一端子和第二端子以及将第一端子和第二端子互连的布线 。 驱动器IC还包括检测第一凸块和第二凸块之间的电阻的电阻检测电路。

公开(公告)号：US08786109B2

公开(公告)日：2014-07-22

申请号：US13793241

申请日：2013-03-11

Applicant: Chipmos Technologies Inc.

Inventor： Chung-Pang Chi

IPC: H01L23/52 ,  H01L23/498 ,  H01L23/00 ,  H01L21/768

CPC classification number: H01L23/49811 ,  H01L21/768 ,  H01L23/528 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05553 ,  H01L2224/061 ,  H01L2224/06163 ,  H01L2224/11462 ,  H01L2224/11472 ,  H01L2224/13012 ,  H01L2224/13022 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/141 ,  H01L2224/14153 ,  H01L2924/381 ,  H01L2224/05552 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: A conductive structure for a semiconductor chip and a method for forming the conductive structure are provided. The semiconductor chip comprises a plurality of first pads and second pads. The pad area is defined with a first area, a second area and a third area, wherein the first area is located between the second area and the third area. Each of the first pads and the second pads are interlaced to each other on the first area. The conductive structure comprises a plurality of conductive bumps formed on each of the first pads and the second pads respectively to electrically connect with each of the first pads and the second pads. Each of the conductive bumps has a first bump-width disposed on the first area and a second bump-width disposed on one of the second and third areas in which the first bump-width is shorter than the second bump-width.

Abstract translation: 提供了一种用于半导体芯片的导电结构和用于形成导电结构的方法。 半导体芯片包括多个第一焊盘和第二焊盘。 焊盘区域被限定有第一区域，第二区域和第三区域，其中第一区域位于第二区域和第三区域之间。 第一焊盘和第二焊盘中的每一个在第一区域上彼此交错。 导电结构包括分别形成在每个第一焊盘和第二焊盘上的多个导电凸块，以与第一焊盘和第二焊盘中的每一个电连接。 每个导电凸块具有设置在第一区域上的第一凸起宽度和设置在第一凸起宽度比第二凸起宽度短的第二和第三区域中的一个上的第二凸起宽度。