公开(公告)号：US20160064359A1

公开(公告)日：2016-03-03

申请号：US14935105

申请日：2015-11-06

Applicant: SK hynix Inc.

Inventor： Jong Hoon KIM ,  Han Jun BAE

IPC: H01L25/065

CPC classification number: H01L25/0657 ,  H01L23/3128 ,  H01L23/3171 ,  H01L23/481 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/0557 ,  H01L2224/05605 ,  H01L2224/05609 ,  H01L2224/05611 ,  H01L2224/05613 ,  H01L2224/05616 ,  H01L2224/05618 ,  H01L2224/05623 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/11462 ,  H01L2224/13016 ,  H01L2224/13017 ,  H01L2224/13147 ,  H01L2224/16146 ,  H01L2224/16147 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/81203 ,  H01L2224/81898 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/15311 ,  H01L2224/81

Abstract: Stack packages are provided. The stack package includes a first chip configured to include a first chip body having a top surface and a bottom surface, first through electrodes penetrating the first chip body, and an insulation layer disposed on the bottom surface of the first chip body, and first bumps disposed on the top surface of the first chip body, and a second chip configured to include a second chip body having a top surface and a bottom surface, and second bumps disposed on the top surface of the second chip body. The first and second chips are vertically stacked such that the top surface of the second chip body is directly attached to the first insulation layer and the second bumps of the second chip penetrate the first insulation layer of the first chip to pierce the first through electrodes of the first chip.

Abstract translation: 提供堆栈包。 堆叠封装包括第一芯片，其构造成包括具有顶表面和底表面的第一芯片主体，第一穿透电极穿过第一芯片主体的绝缘层，以及设置在第一芯片主体的底表面上的绝缘层， 设置在第一芯片主体的上表面上，第二芯片构造成包括具有顶表面和底表面的第二芯片主体，以及设置在第二芯片主体的顶表面上的第二凸块。 第一芯片和第二芯片被垂直堆叠，使得第二芯片主体的顶表面直接附接到第一绝缘层，并且第二芯片的第二凸块穿透第一芯片的第一绝缘层以刺穿第一芯片主体的第一穿透电极 第一个芯片。

公开(公告)号：US20160027751A1

公开(公告)日：2016-01-28

申请号：US14686775

申请日：2015-04-14

Applicant: Soon-Bum KIM ,  Tae-Eun KIM ,  Eun-Hye PARK

Inventor： Soon-Bum KIM ,  Tae-Eun KIM ,  Eun-Hye PARK

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L24/11 ,  H01L24/16 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05567 ,  H01L2224/05573 ,  H01L2224/05609 ,  H01L2224/05613 ,  H01L2224/05618 ,  H01L2224/0562 ,  H01L2224/05623 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05649 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/05671 ,  H01L2224/05672 ,  H01L2224/05681 ,  H01L2224/11003 ,  H01L2224/1111 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/13007 ,  H01L2224/13017 ,  H01L2224/13021 ,  H01L2224/13076 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13118 ,  H01L2224/13123 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13149 ,  H01L2224/13157 ,  H01L2224/13164 ,  H01L2224/13166 ,  H01L2224/13169 ,  H01L2224/13172 ,  H01L2224/13181 ,  H01L2224/13565 ,  H01L2224/13686 ,  H01L2224/16058 ,  H01L2224/16503 ,  H01L2224/81193 ,  H01L2224/8181 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/053

Abstract: Provided is a semiconductor device having a high-reliability solder joint. The semiconductor device includes a high-temperature solder formed on a conductive pad. A low-temperature solder having a lower melting point than the high-temperature solder is formed on the high-temperature solder. A barrier layer is formed between the high-temperature solder and the low-temperature solder. An Sn content of the high-temperature solder is higher than that of the low-temperature solder.

Abstract translation: 提供具有高可靠性焊点的半导体器件。 半导体器件包括形成在导电焊盘上的高温焊料。 在高温焊料上形成熔点低于高温焊料的低温焊料。 在高温焊料和低温焊料之间形成阻挡层。 高温焊料的Sn含量高于低温焊料。

公开(公告)号：US09214410B2

公开(公告)日：2015-12-15

申请号：US14245618

申请日：2014-04-04

Applicant: SK hynix Inc.

Inventor： Jong Hoon Kim ,  Han Jun Bae

IPC: H01L23/48 ,  H01L25/00 ,  H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L25/18

CPC classification number: H01L25/0657 ,  H01L23/3128 ,  H01L23/3171 ,  H01L23/481 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/0557 ,  H01L2224/05605 ,  H01L2224/05609 ,  H01L2224/05611 ,  H01L2224/05613 ,  H01L2224/05616 ,  H01L2224/05618 ,  H01L2224/05623 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/11462 ,  H01L2224/13016 ,  H01L2224/13017 ,  H01L2224/13147 ,  H01L2224/16146 ,  H01L2224/16147 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/81203 ,  H01L2224/81898 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/15311 ,  H01L2224/81

Abstract: Stack packages are provided. The stack package includes a first chip and a second chip. The first chip includes a first chip body, first through electrodes penetrating the first chip body, and an insulation layer disposed on a bottom surface of the first chip body. The second chip includes a second chip body and bumps disposed on a top surface of the second chip body. The first and second chips are vertically stacked such that the bumps penetrate the insulation layer to pierce the first through electrodes and the top surface of the second chip body directly contacts the insulation layer. Related fabrication methods, electronic systems and memory cards are also provided.

Abstract translation: 提供堆栈包。 堆叠包装包括第一芯片和第二芯片。 第一芯片包括第一芯片体，穿过第一芯片体的第一穿透电极和设置在第一芯片主体的底表面上的绝缘层。 第二芯片包括设置在第二芯片主体的顶表面上的第二芯片体和凸块。 第一和第二芯片垂直堆叠，使得凸块穿透绝缘层以刺穿第一通孔，第二芯片体的顶表面直接接触绝缘层。 还提供了相关的制造方法，电子系统和存储卡。

公开(公告)号：US09142522B2

公开(公告)日：2015-09-22

申请号：US13307849

申请日：2011-11-30

Applicant: Xusheng Bao ,  Ma Phoo Pwint Hlaing ,  Jian Zuo

Inventor： Xusheng Bao ,  Ma Phoo Pwint Hlaing ,  Jian Zuo

IPC: H01L23/485 ,  H01L21/768 ,  H01L23/00

CPC classification number: H01L24/14 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/94 ,  H01L2224/02125 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02331 ,  H01L2224/02375 ,  H01L2224/02377 ,  H01L2224/02381 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/05018 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05082 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05171 ,  H01L2224/05173 ,  H01L2224/05187 ,  H01L2224/05558 ,  H01L2224/05567 ,  H01L2224/05569 ,  H01L2224/05583 ,  H01L2224/05613 ,  H01L2224/05624 ,  H01L2224/05666 ,  H01L2224/05687 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11901 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/14131 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2224/0231 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/01028 ,  H01L2924/01079 ,  H01L2924/01047 ,  H01L2924/04953 ,  H01L2924/01074 ,  H01L2924/01007 ,  H01L2924/01023 ,  H01L2924/04941 ,  H01L2924/01082 ,  H01L2224/11849 ,  H01L2224/11 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A semiconductor device has a semiconductor wafer with a plurality of semiconductor die. A first conductive layer is formed over a surface of the wafer. A first insulating layer is formed over the surface of the wafer and first conductive layer. A second conductive layer has first and second segments formed over the first insulating layer. A second insulating layer is formed over the first insulating layer and second conductive layer. A UBM layer is formed over the second insulating layer and the first segment of the second conductive layer. A first bump is formed over the UBM layer. The first bump is electrically connected to the second segment and electrically isolated from the first segment of the second conductive layer. A second bump is formed over the surface of the wafer and electrically connected to the first segment of the second conductive layer.

Abstract translation: 半导体器件具有带有多个半导体管芯的半导体晶片。 在晶片的表面上形成第一导电层。 在晶片和第一导电层的表面上形成第一绝缘层。 第二导电层具有形成在第一绝缘层上的第一和第二部分。 在第一绝缘层和第二导电层上形成第二绝缘层。 UBM层形成在第二绝缘层和第二导电层的第一段之上。 在UBM层上形成第一凸点。 第一凸起电连接到第二段并与第二导电层的第一段电隔离。 第二凸起形成在晶片的表面上并电连接到第二导电层的第一段。

公开(公告)号：US09024441B2

公开(公告)日：2015-05-05

申请号：US13484289

申请日：2012-05-31

Applicant: Yu-Min Lin ,  Chau-Jie Zhan ,  Tao-Chih Chang

Inventor： Yu-Min Lin ,  Chau-Jie Zhan ,  Tao-Chih Chang

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L24/13 ,  H01L23/49816 ,  H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05552 ,  H01L2224/05559 ,  H01L2224/05572 ,  H01L2224/05613 ,  H01L2224/05618 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/05684 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/115 ,  H01L2224/11502 ,  H01L2224/11848 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/11906 ,  H01L2224/13076 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13118 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/13171 ,  H01L2224/13184 ,  H01L2224/16145 ,  H01L2224/16238 ,  H01L2224/16503 ,  H01L2224/16507 ,  H01L2224/81097 ,  H01L2224/81193 ,  H01L2224/8181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2224/1146

Abstract: A bump structure includes a substrate, a pad, an electrode and a protruding electrode. The pad is disposed on the substrate. The electrode is formed by a first metal material and disposed on the pad. The protruding electrode is formed by a second metal material and disposed on the electrode, wherein a cross-sectional area of the protruding electrode is less than a cross-sectional area of the electrode.

Abstract translation: 凸块结构包括基板，焊盘，电极和突出电极。 衬垫设置在衬底上。 电极由第一金属材料形成并设置在焊盘上。 突起电极由第二金属材料形成并设置在电极上，其中突出电极的横截面面积小于电极的横截面面积。

公开(公告)号：US20150115440A1

公开(公告)日：2015-04-30

申请号：US14592576

申请日：2015-01-08

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Yuichi HIGUCHI

IPC: H01L25/065 ,  H01L23/48 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L21/563 ,  H01L23/481 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/02372 ,  H01L2224/0239 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03614 ,  H01L2224/03912 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/05011 ,  H01L2224/05012 ,  H01L2224/05015 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05187 ,  H01L2224/05551 ,  H01L2224/05552 ,  H01L2224/05555 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05559 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05582 ,  H01L2224/05609 ,  H01L2224/05611 ,  H01L2224/05613 ,  H01L2224/05617 ,  H01L2224/05618 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/05666 ,  H01L2224/05684 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/13014 ,  H01L2224/13017 ,  H01L2224/13019 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13117 ,  H01L2224/13118 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13157 ,  H01L2224/13166 ,  H01L2224/13184 ,  H01L2224/16014 ,  H01L2224/16058 ,  H01L2224/16148 ,  H01L2224/16237 ,  H01L2224/32145 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/8112 ,  H01L2224/81121 ,  H01L2224/8114 ,  H01L2224/81141 ,  H01L2224/81143 ,  H01L2224/81193 ,  H01L2224/81201 ,  H01L2224/83862 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06593 ,  H01L2924/01032 ,  H01L2924/207 ,  H01L2924/2075 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/381 ,  H01L2924/384 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/04953 ,  H01L2924/014 ,  H01L2924/01022 ,  H01L2924/01029

Abstract: A semiconductor device includes multilayer chips in which a first semiconductor chip and a second semiconductor chip are bonded together. A first electrode pad is formed on a principal surface of the first semiconductor chip, and a first bump is formed on the first electrode pad. A second bump is formed on the principal surface of the second semiconductor chip such that the second bump is bonded to the first bump. The first electrode pad has an opening, and the opening and an entire peripheral portion of the opening form a stepped shape form a stepped shape. The first bump has a recessed shape that is recessed at a center thereof and covers the stepped shape.

Abstract translation: 半导体器件包括其中第一半导体芯片和第二半导体芯片结合在一起的多层芯片。 第一电极焊盘形成在第一半导体芯片的主表面上，并且在第一电极焊盘上形成第一突起。 在第二半导体芯片的主表面上形成第二凸起，使得第二凸块与第一凸块接合。 第一电极焊盘具有开口，并且开口和形成台阶状的开口的整个周边部分形成阶梯形状。 第一凸块具有在其中心凹陷并且覆盖阶梯形状的凹陷形状。

公开(公告)号：US09006032B2

公开(公告)日：2015-04-14

申请号：US14212233

申请日：2014-03-14

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jung Wei Cheng ,  Tsung-Ding Wang ,  Chien-Hsun Lee ,  Chun-Chih Chuang

IPC: H01L21/00 ,  H01L23/02 ,  H01L25/065 ,  H01L23/31 ,  H01L23/00 ,  H01L25/10 ,  H01L23/498

CPC classification number: H01L24/81 ,  H01L21/56 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/49811 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L24/85 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05557 ,  H01L2224/05571 ,  H01L2224/05611 ,  H01L2224/05613 ,  H01L2224/05616 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/06155 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/81192 ,  H01L2224/85 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/014 ,  H01L2224/05552 ,  H01L2924/00012

Abstract: A method of forming a semiconductor device package includes removing a portion of a first connector and a molding compound surrounding the first connector to form an opening, wherein the first connector is part of a first package, and removing the portion of the first connector comprises forming a surface on the first connector which is at an angle with respect to a top surface of the molding compound. The method further includes placing a second connector in the opening, wherein the second connector is part of a second package having a semiconductor die. The method further includes bonding the second connector to a remaining portion of the first connector.

Abstract translation: 一种形成半导体器件封装的方法包括去除第一连接器的一部分和围绕第一连接器的模制化合物以形成开口，其中第一连接器是第一封装的一部分，并且移除第一连接器的部分包括成形 所述第一连接器上的表面相对于所述模塑料的顶表面成一角度。 该方法还包括将第二连接器放置在开口中，其中第二连接器是具有半导体管芯的第二封装的一部分。 该方法还包括将第二连接器接合到第一连接器的剩余部分。

公开(公告)号：US20140183732A1

公开(公告)日：2014-07-03

申请号：US13916243

申请日：2013-06-12

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Kuei-Wei Huang ,  Wei-Yu Chen ,  Meng-Tse Chen ,  Wei-Hung Lin ,  Ming-Da Cheng ,  Chung-Shi Liu

IPC: H01L23/498 ,  H01L23/00

CPC classification number: H01L25/105 ,  H01L21/4853 ,  H01L21/561 ,  H01L21/563 ,  H01L23/3135 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/538 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/73 ,  H01L24/81 ,  H01L24/94 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05147 ,  H01L2224/05557 ,  H01L2224/056 ,  H01L2224/05611 ,  H01L2224/05613 ,  H01L2224/05616 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05684 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13564 ,  H01L2224/136 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16058 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/1705 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81007 ,  H01L2224/81193 ,  H01L2224/831 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06565 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/014 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/01083 ,  H01L2924/00014

Abstract: The described embodiments of mechanisms of forming a die package and package on package (PoP) structure involve forming a solder paste layer over metal balls of external connectors of a die package. The solder paste layer protects the metal balls from oxidation. In addition, the solder paste layer enables solder to solder bonding with another die package. Further, the solder paste layer moves an intermetallic compound (IMC) layer formed between the solder paste layer and the metal balls below a surface of a molding compound of the die package. Having the IMC layer below the surface strengthens the bonding structure between the two die packages.

Abstract translation: 形成模具封装和封装（PoP）结构的机构的所述实施例涉及在管芯封装的外部连接器的金属球上形成焊膏层。 焊膏层保护金属球免受氧化。 此外，焊膏层能够使焊料与另一个管芯封装焊接。 此外，焊膏层将形成在焊膏层和金属球之间的金属间化合物（IMC）层移动到模具封装的模塑料的表面下方。 使表面下方的IMC层增强了两个管芯封装之间的结合结构。

公开(公告)号：US20130256914A1

公开(公告)日：2013-10-03

申请号：US13586629

申请日：2012-08-15

Applicant: Jung Wei CHENG ,  Tsung-Ding WANG ,  Chien-Hsun LEE ,  Chun-Chih CHUANG

Inventor： Jung Wei CHENG ,  Tsung-Ding WANG ,  Chien-Hsun LEE ,  Chun-Chih CHUANG

IPC: H01L25/00 ,  H01L21/768

CPC classification number: H01L24/81 ,  H01L21/56 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/49811 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L24/85 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05557 ,  H01L2224/05571 ,  H01L2224/05611 ,  H01L2224/05613 ,  H01L2224/05616 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/06155 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/81192 ,  H01L2224/85 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/014 ,  H01L2224/05552 ,  H01L2924/00012

Abstract: The described embodiments of forming bonding structures for package on package involves removing a portion of connectors and molding compound of the lower package. The described bonding mechanisms enable easier placement and alignment of connectors of an upper package to with connector of a lower package. As a result, the process window of the bonding process is wider. In addition, the bonding structures have smoother join profile and planar joint plane. As a result, the bonding structures are less likely to crack and also are less likely to crack. Both the yield and the form factor of the package on package structure are improved.

Abstract translation: 所形成的用于包装在包装上的粘合结构的实施例包括去除连接器的一部分和下封装的模塑料。 所描述的接合机构使得能够更容易地将上部封装的连接器放置和对准到具有较低封装的连接器。 结果，接合过程的过程窗口更宽。 此外，接合结构具有更平滑的接合轮廓和平面接合平面。 结果，接合结构不太可能破裂，也不易破裂。 包装结构上的包装的产量和形状因数均得到改善。

公开(公告)号：US20120028412A1

公开(公告)日：2012-02-02

申请号：US13195128

申请日：2011-08-01

Applicant: Se-young Jeong ,  Ho-jin Lee ,  Ho-geon Song ,  Jae-hyun Phee

Inventor： Se-young Jeong ,  Ho-jin Lee ,  Ho-geon Song ,  Jae-hyun Phee

IPC: H01L21/50 ,  H01L21/768

CPC classification number: H01L21/76898 ,  H01L21/563 ,  H01L23/481 ,  H01L24/03 ,  H01L24/04 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/92 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/03002 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03464 ,  H01L2224/03618 ,  H01L2224/0401 ,  H01L2224/05017 ,  H01L2224/05557 ,  H01L2224/0557 ,  H01L2224/05609 ,  H01L2224/05613 ,  H01L2224/05614 ,  H01L2224/05616 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05649 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/0567 ,  H01L2224/05673 ,  H01L2224/05676 ,  H01L2224/0568 ,  H01L2224/05681 ,  H01L2224/05683 ,  H01L2224/05684 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13118 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13166 ,  H01L2224/13169 ,  H01L2224/13171 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2224/05552

Abstract: A semiconductor apparatus having a through electrode, a semiconductor package, and a method of manufacturing the semiconductor package are provided. The method of includes preparing a substrate including a buried via, the buried via having a first surface at a first end, and the buried via extending from a first substrate surface of the substrate into the substrate; planarizing a second substrate surface of the substrate opposite the first substrate surface to form a through via by exposing a second via surface at a second end of the buried via opposite the first end; forming a conductive capping layer on the exposed second via surface of the through via; and recessing the second substrate surface so that at least a first portion of the through via extends beyond the second substrate surface.

Abstract translation: 提供了具有贯通电极，半导体封装以及半导体封装的制造方法的半导体装置。 该方法包括制备包括掩埋通孔的衬底，所述埋入通孔在第一端具有第一表面，以及所述掩埋通孔从所述衬底的第一衬底表面延伸到所述衬底中; 平行化与第一衬底表面相对的衬底的第二衬底表面以通过在与第一端相对的埋置通孔的第二端处暴露第二通孔表面而形成通孔; 在通孔的暴露的第二通孔表面上形成导电覆盖层; 并且使所述第二衬底表面凹陷，使得所述通孔的至少第一部分延伸超出所述第二衬底表面。