公开(公告)号：US20180151736A1

公开(公告)日：2018-05-31

申请号：US15877563

申请日：2018-01-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shigenobu Maeda ,  Tae-Yong KWON ,  Sang-Su KIM ,  Jae-Hoo PARK

IPC: H01L29/78 ,  H01L21/8234 ,  H01L29/66 ,  H01L27/088 ,  H01L29/165 ,  H01L21/02 ,  H01L29/08 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/161 ,  H01L29/16

CPC classification number: H01L29/7848 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0886 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/785

Abstract: Methods of forming a semiconductor device may include forming a fin-type active pattern that extends in a first direction on a substrate, the fin-type active pattern including a lower pattern on the substrate and an upper pattern on the lower pattern. A field insulating layer is formed on the substrate, the sidewalls of the fin-type active pattern, and a portion upper pattern protruding further away from the substrate than a top surface of the field insulating layer. A dummy gate pattern that intersects the fin-type active pattern and that extends in a second direction that is different from the first direction is formed. The methods include forming dummy gate spacers on side walls of the dummy gate pattern, forming recesses in the fin-type active pattern on both sides of the dummy gate pattern and forming source and drain regions on both sides of the dummy gate pattern.

公开(公告)号：US09966376B2

公开(公告)日：2018-05-08

申请号：US15231134

申请日：2016-08-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Mun-Hyeon Kim ,  Chang-Woo Noh ,  Keun-Hwi Cho ,  Myung-Gil Kang ,  Shigenobu Maeda

IPC: H01L27/092 ,  H01L29/49 ,  H01L29/51 ,  H01L21/8238 ,  H01L27/02

CPC classification number: H01L27/0924 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823871 ,  H01L21/823878 ,  H01L27/0207 ,  H01L27/092 ,  H01L29/49 ,  H01L29/51

Abstract: Disclosed are CMOS device and CMOS inverter. The CMOS device includes a substrate having active lines extending in a first direction and defined by a device isolation layer, the substrate being divided into an NMOS area, a PMOS area and a boundary area interposed between the NMOS and the PMOS areas and having the device isolation layer without the active line, a gate line extending in a second direction across the active lines and having a first gate structure on the active line in the first area, a second gate structure on the active line in the second and a third gate structure on the device isolation layer in the third area. The electrical resistance and parasitic capacitance of the third gate structure are smaller than those of the NMOS and the PMOS gate structures. Accordingly, better AC and DC performance of the CMOS device can be obtained.

公开(公告)号：US20170294355A1

公开(公告)日：2017-10-12

申请号：US15634343

申请日：2017-06-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-Woo KIM ,  Shigenobu Maeda ,  Young-Moon Choi ,  Yong-Bum Kwon ,  Chang-Woo Sohn ,  Do-Sun Lee

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/66

CPC classification number: H01L21/823431 ,  H01L21/823418 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/785

Abstract: Semiconductor devices may include a plurality of active fins each extending in a first direction on a substrate, a gate structure extending on the active fins in a second direction, and a first source/drain layer on first active fins of the active fins adjacent the gate structure. At least one of two opposing sidewalls of a cross-section of the first source/drain layer taken along the second direction may include a curved portion having a slope with respect to an upper surface of the substrate. The slope may decrease from a bottom toward a top thereof.

公开(公告)号：US20170243942A1

公开(公告)日：2017-08-24

申请号：US15591405

申请日：2017-05-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mirco Cantoro ,  Zhenhua Wu ,  Krishna Bhuwalka ,  Sangsu Kim ,  Shigenobu Maeda

IPC: H01L29/267 ,  H01L21/02 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L29/267 ,  H01L21/02524 ,  H01L21/02538 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0642 ,  H01L29/1054 ,  H01L29/1079 ,  H01L29/1606 ,  H01L29/165

Abstract: A semiconductor device includes an active pattern provided on a substrate and a gate electrode crossing over the active pattern. The active pattern includes a first buffer pattern on the substrate, a channel pattern on the first buffer pattern, a doped pattern between the first buffer pattern and the channel pattern, and a second buffer pattern between the doped pattern and the channel pattern. The doped pattern includes graphene injected with an impurity.

公开(公告)号：US09646711B2

公开(公告)日：2017-05-09

申请号：US14676819

申请日：2015-04-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Min Choi ,  Shigenobu Maeda

IPC: G11C5/02 ,  G11C17/16 ,  H01L23/525 ,  H01L27/112

CPC classification number: G11C17/16 ,  H01L23/5252 ,  H01L27/11206 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A memory device includes first through fourth active regions arranged sequentially along a first direction, and which extend along a second direction different from the first direction; a first gate electrode formed on the first through fourth active regions to intersect the first through fourth active regions, and extending along the first direction; a second gate electrode formed on the first through fourth active regions to intersect the first through fourth active regions, extending along the second direction, and arranged so that no other gate electrodes are between the first gate electrode and the second gate electrode in the second direction; the first gate electrode extending between a first end and a second end;a first wiring line which is formed on the first gate electrode; a first strap contact, which connects the first wiring line and the first gate electrode between the first active region and the second active region; and a second strap contact, which connects the first wiring line and the first gate electrode between the third active region and the fourth active region.

公开(公告)号：US20170018645A1

公开(公告)日：2017-01-19

申请号：US15224313

申请日：2016-07-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shigenobu Maeda ,  Tae-Yong Kwon ,  Sang-Su Kim ,  Jae-Hoo Park

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L29/165 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L29/7848 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0886 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/785

Abstract: Methods of forming a semiconductor device may include forming a fin-type active pattern that extends in a first direction on a substrate, the fin-type active pattern including a lower pattern on the substrate and an upper pattern on the lower pattern. A field insulating layer is formed on the substrate, the sidewalls of the fin-type active pattern, and a portion upper pattern protruding further away from the substrate than a top surface of the field insulating layer. A dummy gate pattern that intersects the fin-type active pattern and that extends in a second direction that is different from the first direction is formed. The methods include forming dummy gate spacers on side walls of the dummy gate pattern, forming recesses in the fin-type active pattern on both sides of the dummy gate pattern and forming source and drain regions on both sides of the dummy gate pattern.

Abstract translation: 形成半导体器件的方法可以包括形成在衬底上沿第一方向延伸的鳍式有源图案，鳍型有源图案包括在衬底上的下图案和下图案上的上图案。 场绝缘层形成在衬底上，翅片型有源图案的侧壁和远离衬底的部分上部图案远离场绝缘层的顶表面。 形成与翅片型有源图案相交并且沿与第一方向不同的第二方向延伸的伪栅极图案。 所述方法包括在伪栅极图案的侧壁上形成虚拟栅极间隔物，在虚拟栅极图案的两侧上形成鳍状有源图案中的凹槽，并在虚拟栅极图案的两侧形成源区和漏极区。

公开(公告)号：US09425182B2

公开(公告)日：2016-08-23

申请号：US14791770

申请日：2015-07-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shigenobu Maeda ,  Jeong Hwan Yang

IPC: H01L23/62 ,  H01L29/76 ,  H01L21/8238 ,  H01L27/02 ,  H01L21/8234 ,  H01L27/105 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0922 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/0207 ,  H01L27/092 ,  H01L27/1052 ,  H01L29/0649 ,  H01L29/665 ,  H01L29/7833 ,  H01L29/7842 ,  H01L29/7843 ,  H01L29/7845 ,  H01L29/7848

Abstract: In semiconductor devices in which both NMOS devices and PMOS devices are used to perform in different modes such as analog and digital modes, stress engineering is selectively applied to particular devices depending on their required operational modes. That is, the appropriate mechanical stress, i.e., tensile or compressive, can be applied to and/or removed from devices, i.e., NMOS and/or PMOS devices, based not only on their conductivity type, i.e., n-type or p-type, but also on their intended operational application, for example, analog/digital, low-voltage/high-voltage, high-speed/low-speed, noise-sensitive/noise-insensitive, etc. The result is that performance of individual devices is optimized based on the mode in which they operate. For example, mechanical stress can be applied to devices that operate in high-speed digital settings, while devices that operate in analog or RF signal settings, in which electrical noise such as flicker noise that may be introduced by applied stress may degrade performance, have no stress applied.

公开(公告)号：US09336894B2

公开(公告)日：2016-05-10

申请号：US14753620

申请日：2015-06-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Min Choi ,  Shigenobu Maeda ,  Ji-Hoon Yoon

IPC: G11C17/00 ,  G11C17/08 ,  G11C13/00

CPC classification number: G11C13/004 ,  G11C11/5685 ,  G11C11/5692 ,  G11C13/0007 ,  G11C13/0069 ,  G11C17/165 ,  G11C17/18 ,  G11C2213/53

Abstract: A memory device may include nonvolatile memory cells. A first memory cell of the nonvolatile memory cells may have a first resistance value in a first state and a second memory cell of the nonvolatile memory cells may have a second resistance value less than the first resistance value in a second state. A third memory cell of the nonvolatile memory cells may have a third resistance value less than the first resistance value and greater than the second resistance value in a third state, and a fourth memory cell of the nonvolatile memory cells may have a fourth resistance value less than the third resistance value and greater than the second resistance value in a fourth state.

Abstract translation: 存储器件可以包括非易失性存储器单元。 非易失性存储器单元的第一存储单元可以具有第一状态的第一电阻值，并且非易失性存储单元的第二存储单元可具有小于第二状态的第一电阻值的第二电阻值。 非易失性存储单元的第三存储单元可具有小于第一电阻值的第三电阻值并且大于第三状态中的第二电阻值，并且非易失性存储单元的第四存储单元可具有较小的第四电阻值 大于第四电阻值且大于第四电阻值。

公开(公告)号：US09330981B2

公开(公告)日：2016-05-03

申请号：US14460081

申请日：2014-08-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shigenobu Maeda ,  Hyun-pil Noh ,  Choong-ho Lee ,  Seog-heon Ham

IPC: H01L21/77 ,  H01L21/8236 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L29/66 ,  H01L27/00 ,  H01L25/00

CPC classification number: H01L21/8236 ,  H01L21/77 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823462 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823857 ,  H01L25/00 ,  H01L27/00 ,  H01L27/0883 ,  H01L29/66545 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided are a semiconductor device including a high voltage transistor and a low voltage transistor and a method of manufacturing the same. The semiconductor device includes a semiconductor substrate including a high voltage region and a low voltage region; a high voltage transistor formed in the high voltage region and including a first active region, a first source/drain region, a first gate insulating layer, and a first gate electrode; and a low voltage transistor formed in the low voltage region and including a second active region, a second source/drain region, a second gate insulating layer, and a second gate electrode. The second source/drain region has a smaller thickness than a thickness of the first source/drain region.

Abstract translation: 提供了包括高压晶体管和低压晶体管的半导体器件及其制造方法。 半导体器件包括：包括高电压区域和低电压区域的半导体衬底; 形成在高电压区域中并包括第一有源区，第一源极/漏极区，第一栅极绝缘层和第一栅电极的高压晶体管; 以及形成在所述低电压区域中并包括第二有源区，第二源极/漏极区，第二栅极绝缘层和第二栅电极的低电压晶体管。 第二源极/漏极区域的厚度小于第一源极/漏极区域的厚度。

公开(公告)号：US20140117414A1

公开(公告)日：2014-05-01

申请号：US14150166

申请日：2014-01-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shigenobu Maeda ,  Jeong Hwan Yang ,  Junga Choi

IPC: H01L29/78

CPC classification number: H01L29/7854 ,  H01L29/045 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7855

Abstract: In a semiconductor capable of reducing NBTI and a method for manufacturing the same, a multi-gate transistor includes an active region, gate dielectric, channels in the active region, and gate electrodes, and is formed on a semiconductor wafer. The active region has a top and side surfaces, and is oriented in a first direction. The gate dielectric is formed on the top and side surfaces of the active region. The channels are formed in the top and side surfaces of the active region. The gate electrodes are formed on the gate dielectric corresponding to the channels and aligned perpendicular to the active region such that current flows in the first direction. In one aspect of the invention, an SOI layer having a second orientation indicator in a second direction is formed on a supporting substrate having a first orientation indicator in a first direction.

Abstract translation: 在能够减少NBTI的半导体及其制造方法中，多栅极晶体管包括有源区，栅极电介质，有源区中的沟道和栅电极，并形成在半导体晶片上。 有源区具有顶表面和侧表面，并且在第一方向上定向。 栅电介质形成在有源区的顶表面和侧表面上。 通道形成在有源区域的顶表面和侧表面中。 栅极电极形成在对应于沟道的栅极电介质上并垂直于有源区域排列，使得电流在第一方向上流动。 在本发明的一个方面中，在具有第一方向的第一取向指示器的支撑基板上形成具有第二方向的第二取向指示器的SOI层。