公开(公告)号：US09336863B2

公开(公告)日：2016-05-10

申请号：US14320024

申请日：2014-06-30

Applicant: QUALCOMM Incorporated ,  Industry-Academic Cooperation Foundation, Yonsei University

Inventor： Seong-Ook Jung ,  Younghwi Yang ,  Stanley Seungchul Song ,  Choh Fei Yeap ,  Zhongze Wang

IPC: G11C11/417 ,  G11C5/06 ,  G11C7/00 ,  G11C8/16 ,  G11C5/02 ,  G11C11/419 ,  G11C11/412 ,  G11C8/14 ,  G11C7/20

CPC classification number: G11C11/419 ,  G11C5/02 ,  G11C7/00 ,  G11C7/20 ,  G11C8/14 ,  G11C8/16 ,  G11C11/412 ,  G11C11/417

Abstract: A static random-access memory (SRAM) memory cell includes a pair of cross-coupled inverters and a gating transistor coupled to a first node of a first inverter of the pair of cross-coupled inverters. A gate of the gating transistor is coupled to a first wordline. The gating transistor is configured to selectively couple a bitline to the first node of the first inverter responsive to a first wordline signal. The first inverter has a second node coupled to a second wordline. The first wordline and the second wordline are each independently controllable.

Abstract translation: 静态随机存取存储器（SRAM）存储单元包括一对交叉耦合的反相器和耦合到该对交叉耦合的反相器的第一反相器的第一节点的选通晶体管。 门控晶体管的栅极耦合到第一字线。 门控晶体管被配置为响应于第一字线信号而选择性地将位线耦合到第一逆变器的第一节点。 第一反相器具有耦合到第二字线的第二节点。 第一个字线和第二个字线都是可以独立控制的。

公开(公告)号：US20160086805A1

公开(公告)日：2016-03-24

申请号：US14626293

申请日：2015-02-19

Applicant: QUALCOMM Incorporated

Inventor： Jeffrey Junhao Xu ,  Zhongze Wang ,  Kern Rim ,  Stanley Seungchul Song ,  Choh Fei Yeap

IPC: H01L21/28 ,  H01L21/306 ,  H01L29/49 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L21/28079 ,  H01L21/30604 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823871 ,  H01L27/0924 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7848 ,  H01L29/785

Abstract: A particular semiconductor device includes a substrate, a source contact, a drain contact, and a metal-gate. The substrate includes a source region, a drain region, and a channel. The source contact is coupled to the source region. The drain contact is coupled to the drain region. The metal-gate is coupled to the channel. The metal-gate includes an amorphous metal layer.

Abstract translation: 特定的半导体器件包括衬底，源极接触，漏极接触和金属栅极。 衬底包括源极区，漏极区和沟道。 源极触点耦合到源极区域。 漏极触点耦合到漏极区域。 金属栅极耦合到通道。 金属栅极包括非晶金属层。

公开(公告)号：US09263279B2

公开(公告)日：2016-02-16

申请号：US13864344

申请日：2013-04-17

Applicant: QUALCOMM Incorporated

Inventor： John J. Zhu ,  Zhongze Wang ,  Da Yang

IPC: H01L21/28 ,  H01L21/31 ,  H01L21/469 ,  H01L21/283 ,  H01L21/768 ,  H01L23/50 ,  G03F7/20 ,  H01L23/00

CPC classification number: H01L21/76894 ,  G03F7/7045 ,  G03F7/70466 ,  H01L21/28123 ,  H01L21/283 ,  H01L21/31 ,  H01L21/469 ,  H01L21/76892 ,  H01L21/76895 ,  H01L23/50 ,  H01L24/27 ,  H01L24/31 ,  H01L2924/0002 ,  H01L2924/12042 ,  H01L2924/00

Abstract: Features are fabricated on a semiconductor chip. The features are smaller than the threshold of the lithography used to create the chip. A method includes patterning a first portion of a feature (such as a local interconnect) and a second portion of the feature to be separated by a predetermined distance, such as a line tip to tip space or a line space. The method further includes patterning the first portion with a cut mask to form a first sub-portion (e.g., a contact) and a second sub-portion. A dimension of the first sub-portion is less than a dimension of a second predetermined distance, which may be a line length resolution of a lithographic process having a specified width resolution. A feature of a semiconductor device includes a first portion and a second portion having a dimension less than a lithographic resolution of the first portion.

Abstract translation: 特征是在半导体芯片上制造的。 这些特征小于用于制造芯片的光刻的阈值。 一种方法包括图案化特征（例如局部互连）的第一部分和要被分离预定距离的特征的第二部分，例如线尖到尖端空间或线空间。 该方法还包括用切割掩模图案化第一部分以形成第一子部分（例如，接触）和第二子部分。 第一子部分的尺寸小于第二预定距离的尺寸，其可以是具有指定宽度分辨率的光刻工艺的线长分辨率。 半导体器件的特征包括具有小于第一部分的光刻分辨率的尺寸的第一部分和第二部分。

公开(公告)号：US20160020220A1

公开(公告)日：2016-01-21

申请号：US14495507

申请日：2014-09-24

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Jeffrey Junhao Xu ,  Xiao Lu ,  Bin Yang ,  Jun Yuan ,  Xiaonan Chen ,  Zhongze Wang

IPC: H01L27/115 ,  G11C16/10 ,  G11C16/26 ,  H01L29/792

CPC classification number: H01L29/792 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/26 ,  G11C17/18 ,  H01L27/11206 ,  H01L29/4234 ,  H01L29/513 ,  H01L29/517

Abstract: An apparatus includes a metal gate, a substrate material, and an oxide layer between the metal gate and the substrate material. The oxide layer includes a hafnium oxide layer contacting the metal gate and a silicon dioxide layer contacting the substrate material and contacting the hafnium oxide layer. The metal gate, the substrate material, and the oxide layer are included in a one-time programmable (OTP) memory device. The OTP memory device includes a transistor. A non-volatile state of the OTP memory device is based on a threshold voltage shift of the OTP memory device.

Abstract translation: 一种装置包括金属栅极，衬底材料和金属栅极和衬底材料之间的氧化物层。 氧化物层包括与金属栅极接触的氧化铪层和与衬底材料接触并与氧化铪层接触的二氧化硅层。 金属栅极，衬底材料和氧化物层包括在一次性可编程（OTP）存储器件中。 OTP存储器件包括晶体管。 OTP存储器件的非易失性状态基于OTP存储器件的阈值电压偏移。

公开(公告)号：US20150035019A1

公开(公告)日：2015-02-05

申请号：US13956398

申请日：2013-08-01

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Zhongze Wang ,  Choh fei Yeap

IPC: H01L21/02 ,  H01L29/78 ,  H01L29/10

CPC classification number: H01L27/1207 ,  H01L21/02365 ,  H01L21/823431 ,  H01L21/8258 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/1033 ,  H01L29/1037 ,  H01L29/16 ,  H01L29/20 ,  H01L29/785

Abstract: A method of forming fins of different materials includes providing a substrate with a layer of a first material having a top surface, masking a first portion of the substrate leaving a second portion of the substrate exposed, etching a first opening at the second portion, forming a body of a second material in the opening to a level of the top surface of the layer of the first material, removing the mask, and forming fins of the first material at the first portion and forming fins of the second material at the second portion. A finFET device having fins formed of at least two different materials is also disclosed.

Abstract translation: 形成不同材料的散热片的方法包括：提供具有顶表面的第一材料层的衬底，掩蔽衬底的第一部分，留下衬底的第二部分，蚀刻第二部分的第一开口，形成 在所述开口中的第二材料的主体到所述第一材料的所述层的顶表面的高度，去除所述掩模，以及在所述第一部分处形成所述第一材料的翅片，并在所述第二部分处形成所述第二材料的翅片 。 还公开了具有由至少两种不同材料形成的翅片的finFET器件。

公开(公告)号：US20140269020A1

公开(公告)日：2014-09-18

申请号：US13842263

申请日：2013-03-15

Applicant: QUALCOMM INCORPORATED

Inventor： Stanley Seungchul Song ,  Zhongze Wang

IPC: G11C11/4074 ,  G06F17/50 ,  G11C14/00

CPC classification number: G11C11/4074 ,  G06F17/5072 ,  G11C5/147 ,  G11C7/04 ,  G11C11/413 ,  G11C11/417

Abstract: A method includes measuring a temperature of a sensor associated with a memory array. The method also includes calculating, at a voltage regulating device, an operating voltage based on the temperature and based on fabrication data associated with the memory array. The method further includes regulating, at the voltage regulating device, a voltage provided to the memory array based on the operating voltage.

Abstract translation: 一种方法包括测量与存储器阵列相关联的传感器的温度。 该方法还包括在电压调节装置处基于温度和基于与存储器阵列相关联的制造数据来计算工作电压。 该方法还包括在电压调节装置处基于工作电压调节提供给存储器阵列的电压。

公开(公告)号：US12074109B2

公开(公告)日：2024-08-27

申请号：US17648981

申请日：2022-01-26

Applicant: QUALCOMM Incorporated

Inventor： Mustafa Badaroglu ,  Zhongze Wang

IPC: H01L23/528 ,  H01L21/762 ,  H01L21/8238 ,  H01L23/522 ,  H01L27/092

CPC classification number: H01L23/5286 ,  H01L21/76224 ,  H01L21/823871 ,  H01L21/823878 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/092

Abstract: An integrated circuit includes a trench power rail to reduce resistance in a power rail or avoid an increase in resistance of a power rail as a result of the metal tracks being reduced in size as the technology node size is reduced. The trench power rail is formed in isolation regions between cell circuits. A cell isolation trench in the isolation region provides additional volume in which to dispose additional metal material for forming the trench power rail to increase its cross-sectional area. The trench power rail extends through a via layer to a metal layer, including signal interconnects. The trench power rail extends in a width direction out of the cell isolation trench in the via layer to couple to trench contacts of the adjacent cell circuits without vertical interconnect accesses (vias). A high-K dielectric layer can selectively isolate the trench power rail from the cell circuits.

公开(公告)号：US11631455B2

公开(公告)日：2023-04-18

申请号：US17152564

申请日：2021-01-19

Applicant: QUALCOMM Incorporated

Inventor： Seyed Arash Mirhaj ,  Xiaonan Chen ,  Ankit Srivastava ,  Sameer Wadhwa ,  Zhongze Wang

IPC: G11C11/419 ,  G06F7/544

Abstract: A compute-in-memory bitcell is provided that includes a pair of cross-coupled inverters for storing a stored bit. The compute-in-memory bitcell includes a logic gate for multiplying the stored bit with an input vector bit. An output node for the logic gate connects to a second plate of a capacitor. A first plate of the capacitor connects to a read bit line. A write driver controls a power supply voltage to the cross-coupled inverters, the first switch, and the second switch to capacitively write the stored bit to the pair of cross-coupled inverters.

公开(公告)号：US10290352B2

公开(公告)日：2019-05-14

申请号：US14633793

申请日：2015-02-27

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Xiao Lu ,  Xiaonan Chen ,  Zhongze Wang

IPC: G11C16/10 ,  H01L29/792 ,  G11C16/04 ,  G11C17/16 ,  G11C17/18 ,  H01L29/423 ,  H01L27/112 ,  G11C17/14

Abstract: A semiconductor device for a one-time programmable (OTP) memory according to some examples of the disclosure includes a gate, a dielectric region below the gate, a source terminal below the dielectric region and offset to one side, a drain terminal below the dielectric region and offset to an opposite side from the source terminal, a drain side charge trap in the dielectric region capable of programming the semiconductor device, and a source side charge trap in the dielectric region opposite the drain side charge trap and capable of programming the semiconductor device.

公开(公告)号：US09941154B2

公开(公告)日：2018-04-10

申请号：US15390405

申请日：2016-12-23

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Choh Fei Yeap ,  Zhongze Wang ,  John Jianhong Zhu

IPC: H01L21/033 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/66

CPC classification number: H01L21/76816 ,  G06F17/5068 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/66 ,  H01L2223/6677 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In a particular embodiment, a method includes forming a second hardmask layer adjacent to a first sidewall structure and adjacent to a mandrel of a semiconductor device. A top portion of the mandrel is exposed prior to formation of the second hardmask layer. The method further includes removing the first sidewall structure to expose a first portion of a first hardmask layer. The method also includes etching the first portion of the first hardmask layer to expose a second portion of a dielectric material. The method also includes etching the second portion of the dielectric material to form a first trench. The method also includes forming a first metal structure within the first trench.