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    Integrated device comprising a CMOS structure comprising well-less transistors
    3.
    发明授权
    Integrated device comprising a CMOS structure comprising well-less transistors 有权

    公开(公告)号：US11502079B2

    公开(公告)日：2022-11-15

    申请号：US16817446

    申请日：2020-03-12

    Applicant: QUALCOMM Incorporated

    Inventor： Stanley Seungchul Song ,  Hyunwoo Park ,  Peijie Feng

    IPC: H01L27/092 ,  H01L29/06

    Abstract: An integrated device that includes a substrate, a first transistor, and a second transistor. The second transistor is configured to be coupled to the first transistor. The first transistor is configured to operate as a N-type channel metal oxide semiconductor transistor (NMOS) transistor. The first transistor includes a dielectric layer disposed over the substrate; a first source disposed over the dielectric layer; a first drain disposed over the dielectric layer; a first plurality of channels coupled to the first source and the first drain; and a first gate surrounding the plurality of channels. The second transistor is configured to operate as a P-type channel metal oxide semiconductor transistor (PMOS). The second transistor includes the dielectric layer; a second source disposed over the dielectric layer; a second drain disposed over the dielectric layer; a second plurality of channels coupled to the second source and the second drain; and a second gate.

    GATE-ALL-AROUND (GAA) TRANSISTORS WITH SHALLOW SOURCE/DRAIN REGIONS AND METHODS OF FABRICATING THE SAME
    5.
    发明申请
    GATE-ALL-AROUND (GAA) TRANSISTORS WITH SHALLOW SOURCE/DRAIN REGIONS AND METHODS OF FABRICATING THE SAME 有权

    公开(公告)号：US20220037493A1

    公开(公告)日：2022-02-03

    申请号：US16944624

    申请日：2020-07-31

    Applicant: QUALCOMM Incorporated

    Inventor： Peijie Feng ,  Stanley Seungchul Song ,  Kern Rim

    IPC: H01L29/423 ,  H01L29/06 ,  H01L29/78 ,  H01L29/167

    Abstract: Gate-all-around (GAA) transistors with shallow source/drain regions and methods of fabricating the same provide a GAA transistor that includes one or more channels positioned between a source region and a drain region. The one or more channels, which may be nanowire, nanosheet, or nanoslab semiconductors, are surrounded along a longitudinal axis by gate material. At a first end of the channel is a source region and at an opposite end of the channel is a drain region. To reduce parasitic capacitance between a bottom gate and the source and drain regions, a filler material is provided adjacent the bottom gate, and the source and drain regions are grown on top of the filler material. In this fashion, the bottom gate does not abut the source region or the drain region, reducing geometries which would contribute to parasitic capacitance.

    Cell circuits formed in circuit cells employing offset gate cut areas in a non-active area for routing transistor gate cross-connections
    6.
    发明授权
    Cell circuits formed in circuit cells employing offset gate cut areas in a non-active area for routing transistor gate cross-connections 有权

    公开(公告)号：US11152347B2

    公开(公告)日：2021-10-19

    申请号：US15952638

    申请日：2018-04-13

    Applicant: QUALCOMM Incorporated

    Inventor： Stanley Seungchul Song ,  Kern Rim ,  John Jianhong Zhu ,  Da Yang

    IPC: H01L27/02 ,  H01L23/48 ,  H03K3/3562 ,  H01L27/118

    Abstract: Cell circuits formed in circuit cells employing offset gate cut areas in a non-active area for routing transistor gate cross-connections. In exemplary aspects disclosed herein, to allow cross-connections to be made across different gates between PMOS and NMOS transistors formed in the circuit cell, cut areas in the circuit cell are located in different horizontal routing tracks and offset from each other in the direction of longitudinal axes of gates. Gate cross-connections can be routed around offset gate cut areas and coupled to active gates to form gate cross-connections. In this manner, fewer metal layers may be required to provide such cross-connections in the circuit cell, thus reducing area. Further, gate contacts of cross-connected gates can be formed as gate contacts over active areas (GCOAs) in diffusion areas of the circuit cell, thus facilitating easier routing of interconnections in non-diffusion area of the circuit cell for further ease of routing.

    CELL CIRCUITS FORMED IN CIRCUIT CELLS EMPLOYING OFFSET GATE CUT AREAS IN A NON-ACTIVE AREA FOR ROUTING TRANSISTOR GATE CROSS-CONNECTIONS
    9.
    发明申请
    CELL CIRCUITS FORMED IN CIRCUIT CELLS EMPLOYING OFFSET GATE CUT AREAS IN A NON-ACTIVE AREA FOR ROUTING TRANSISTOR GATE CROSS-CONNECTIONS 审中-公开

    公开(公告)号：US20190319022A1

    公开(公告)日：2019-10-17

    申请号：US15952638

    申请日：2018-04-13

    Applicant: QUALCOMM Incorporated

    Inventor： Stanley Seungchul Song ,  Kern Rim ,  John Jianhong Zhu ,  Da Yang

    IPC: H01L27/02 ,  H01L27/118 ,  H03K3/3562 ,  H01L23/48

    Abstract: Cell circuits formed in circuit cells employing offset gate cut areas in a non-active area for routing transistor gate cross-connections. In exemplary aspects disclosed herein, to allow cross-connections to be made across different gates between PMOS and NMOS transistors formed in the circuit cell, cut areas in the circuit cell are located in different horizontal routing tracks and offset from each other in the direction of longitudinal axes of gates. Gate cross-connections can be routed around offset gate cut areas and coupled to active gates to form gate cross-connections. In this manner, fewer metal layers may be required to provide such cross-connections in the circuit cell, thus reducing area. Further, gate contacts of cross-connected gates can be formed as gate contacts over active areas (GCOAs) in diffusion areas of the circuit cell, thus facilitating easier routing of interconnections in non-diffusion area of the circuit cell for further ease of routing.

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