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公开(公告)号：US11768443B2
公开(公告)日：2023-09-26
申请号：US17846294
申请日：2022-06-22
Inventor： Yu-Ching Lee , Yu-Piao Fang
CPC classification number: G03F7/70633 , G03F7/2022 , G03F7/70466 , G03F7/70625 , G03F7/70641 , G03F7/70683 , G03F9/7076 , B82Y20/00
Abstract: Methods for manufacturing a semiconductor structure are provided. A substrate is provided. A metrology target is formed in a layer over the substrate according to a first layer mask and a second layer mask. The metrology target includes a first pattern formed by a plurality of first photonic crystals corresponding to the first layer mask and a second pattern formed by a plurality of second photonic crystals corresponding to the second layer mask. First light is provided to illuminate the metrology target. Second light is received from the metrology target in response to the first light. The second light is analyzed to detect overlay-shift between the first pattern and the second pattern. The first pattern and the second pattern are arranged to cross in one direction in the metrology target.
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2.发明公开公开(公告)号：US20230288812A1
公开(公告)日：2023-09-14
申请号：US18006249
申请日：2021-09-09
Applicant: Applied Materials, Inc.
Inventor： Chi-Ming TSAI
IPC: G03F7/20
CPC classification number: G03F7/2051 , G03F7/70508 , G03F7/70466 , G03F7/70725
Abstract: Embodiments described herein relate to methods of printing double exposure patterns in a lithography environment. The methods include determining a second exposure pattern to be exposed with a first exposure pattern in a lithography process. The second exposure pattern is determined with a rule-based process flow or a lithography model process flow.
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公开(公告)号：US11733606B2
公开(公告)日：2023-08-22
申请号：US16972073
申请日：2019-04-29
Applicant: ASML NETHERLANDS B.V.
CPC classification number: G03F1/70 , G03F7/705 , G03F7/70283 , G03F7/70466 , G03F7/70475
Abstract: A method for assigning features into at least first features and second features, the first features being for at least one first patterning device configured for use in a lithographic process to form corresponding first structures on a substrate and the second features being for at least one second patterning device configured for use in a lithographic process to form corresponding second structures on a substrate, wherein the method including assigning the features into the first features and the second features based on a patterning characteristic of the features.
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公开(公告)号：US11709431B2
公开(公告)日：2023-07-25
申请号：US17642613
申请日：2020-09-15
Applicant: RICHEMONT INTERNATIONAL SA
Inventor： Susana del Carmen Tobenas Borron , Alexis Heraud , Luca Ribetto , Béatrice Wenk , Nelly Socquet
CPC classification number: G03F7/705 , G03F7/70466 , G03F7/70525 , G04B17/066
Abstract: A method for manufacturing a plurality of mechanical resonators (100) in a manufacturing wafer (10), the resonators being intended to be fitted to an adjusting member of a timepiece, the method comprising the following steps: (a) manufacturing a plurality of resonators in at least one reference wafer according to reference specifications, such manufacture comprising at least one lithography step to form patterns of the resonators on or above the reference wafer and a step of machining in the reference plate using the patterns; (b) for the at least one reference plate, establishing a map indicative of the dispersion of stiffnesses of the resonators relative to an average stiffness value; (c) dividing the map into fields and determining a correction to be made to the dimensions of the resonators for at least one of the fields in order to reduce the dispersion; (d) modifying the reference specifications for the lithography step so as to make the corrections to the dimensions for the at least one field in the lithography step; (e) manufacturing resonators in a manufacturing wafer using the modified specifications.
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公开(公告)号：US20230205093A1
公开(公告)日：2023-06-29
申请号：US18114845
申请日：2023-02-27
Inventor： Ken-Hsien HSIEH , Ru-Gun LIU , Wei-Shuo SU
IPC: G03F7/20 , H01L21/311 , G03F1/36 , G03F1/70 , G06F30/398
CPC classification number: G03F7/70466 , H01L21/31144 , G03F1/36 , G03F1/70 , G06F30/398 , G06F2119/18
Abstract: In a method of manufacturing a photo mask used in a semiconductor manufacturing process, a mask pattern layout in which a plurality of patterns are arranged is acquired. The plurality of patterns are converted into a graph having nodes and links. It is determined whether the nodes are colorable by N colors without causing adjacent nodes connected by a link to be colored by a same color, where N is an integer equal to or more than 3. When it is determined that the nodes are colorable by N colors, the nodes are colored with the N colors. The plurality of patterns are classified into N groups based on the N colored nodes. The N groups are assigned to N photo masks. N data sets for the N photo masks are output.
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Patent Agency Ranking
公开(公告)号：US11681228B2
公开(公告)日：2023-06-20
申请号：US16973578
申请日：2018-06-19
Applicant: EV Group E. Thallner GmbH
Inventor： Bernhard Thallner , Boris Povazay
CPC classification number: G03F7/704 , G03F7/2051 , G03F7/70283 , G03F7/70291 , G03F7/70358 , G03F7/70466 , G03F7/70558
Abstract: A method for the exposure of image points of a photosensitive layer comprising a photosensitive material on a substrate by means of an optical system. The method including continuously moving the image points with respect to the optical system; and controlling a plurality of secondary beams by means of the optical system individually for individual exposures of each image point, whereby the secondary beams are put either into an ON state or into an OFF state, wherein a) secondary beams in the ON state produce an individual exposure of the image point assigned to the respective secondary beam and b) secondary beams in the OFF state do not produce any individual exposure of the image point assigned to the respective secondary beam; wherein, for the generation of image points with grey tones n>1, individual exposures are carried out by different secondary beams with individual doses D.
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公开(公告)号：US20180224745A1
公开(公告)日：2018-08-09
申请号：US15943957
申请日：2018-04-03
Applicant: NIKON CORPORATION
Inventor： Yoji WATANABE
CPC classification number: G03F7/70 , G03F7/0035 , G03F7/70466
Abstract: A device manufacturing method includes forming, in a first layer, first line patterns of which longitudinal direction is a first direction; and forming, in a second layer above the first layer, second line patterns of which longitudinal direction is a second direction crossing the first direction, and third line patterns of which longitudinal direction is the second direction and having a etching characteristic different from an etching characteristic of the second line patterns. At least one edge portion of each of the second line patterns and at least one edge portion of each of the third line patterns are adjacent. As viewed from above the second layer, the adjacent at least one edge portions of one of the second and third line patterns are positioned between two adjacent line patterns of the first line pattern.
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公开(公告)号：US20180203341A1
公开(公告)日：2018-07-19
申请号：US15406070
申请日：2017-01-13
Applicant: International Business Machines Corporation
Inventor： John B. Deforge , Bassem M. Hamieh , Terence B. Hook , Theresa A. Newton , Kirk D. Peterson
CPC classification number: G03F7/2022 , G03F1/70 , G03F7/70466
Abstract: After printing common features from a primary mask into a photoresist layer located over a substrate, a functional feature which is suitable for changing functionalities or the configurations of the common features according to a chip design is selected from a library of additional functional features in a secondary mask. The selected functional feature from the secondary mask is printed into the photoresist layer to modify the common features that already exist in the photoresist layer. The selection and printing of functional feature processes can be repeated until a final image corresponding to the chip design is obtained in the photoresist layer.
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公开(公告)号：US09996657B2
公开(公告)日：2018-06-12
申请号：US15221676
申请日：2016-07-28
Inventor： Chun-Chen Chen , Sheng-Hsiung Chen , Fong-Yuan Chang , Shao-Huan Wang
CPC classification number: G06F17/5081 , G03F1/68 , G03F1/70 , G03F7/70466 , G06F17/5072
Abstract: Computer-implemented systems and methods for generating a multiple patterning lithography (MPL) compliant integrated circuit layout are provided. A plurality of integrated circuit (IC) cells are assembled to form an IC layout. The IC layout includes at least two IC cells that abut one another. After the assembling of the IC cells, a decomposition algorithm is executed to assign multiple colors to design shapes within the IC layout. Multiple patterning coloring conflicts are detected in the IC layout after the assigning of the colors to the design shapes. A fixing algorithm is executed, under which a conflict present in two abutting IC cells is fixed by flipping or shifting at least one of the abutting IC cells.
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公开(公告)号：US09989846B2
公开(公告)日：2018-06-05
申请号：US15048719
申请日：2016-02-19
Applicant: Tokyo Electron Limited
Inventor： Anton J. deVilliers , Jeffrey Smith
CPC classification number: G03F7/0035 , G03F7/325 , G03F7/70466 , G03F7/70633
Abstract: Substrate patterning techniques herein protect against overlay misalignment. Techniques include using a combination of relief patterns in which one relief pattern includes openings filled with a particular photoresist and these openings have a width that is insufficient to enable wave propagation of electromagnetic radiation having wavelengths greater than a predetermined threshold wavelength. Accordingly, actinic radiation above a certain wavelength cannot affect the photoresist within these relatively small openings. Photoresist filled within these openings can be removed by specific developers with the openings partially uncovered, which helps ensure features and connections are fabricated as designed.
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