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    Fully self-aligned via with selective bilayer dielectric regrowth
    3.
    发明授权
    Fully self-aligned via with selective bilayer dielectric regrowth 有权

    公开(公告)号：US11705369B2

    公开(公告)日：2023-07-18

    申请号：US17223831

    申请日：2021-04-06

    Applicant: Tokyo Electron Limited

    Inventor： Kandabara Tapily ,  Jeffrey Smith

    IPC: H01L21/768 ,  H01L23/522

    CPC classification number: H01L21/76897 ,  H01L21/76808 ,  H01L21/76816 ,  H01L21/76843 ,  H01L23/5226

    Abstract: A semiconductor device includes conductive structures formed in a first dielectric layer, a conductive cap layer selectively positioned over the conductive structures and the first dielectric layer with a top surface and sidewalls, a second dielectric layer selectively positioned over the first dielectric layer and disposed between the sidewalls of the conductive cap layer, a third dielectric layer selectively positioned over the second dielectric layer and disposed between the sidewalls of the conductive cap layer, a fourth dielectric layer arranged over the conductive structures and the third dielectric layer, and an interconnect structure formed in the fourth dielectric layer. The interconnect structure includes a trench structure and a via structure that is positioned below the trench structure and connected to the trench structure. The via structure includes a first portion positioned over the conductive cap layer and a second portion disposed over the first portion and the third dielectric layer.

    Apparatus and method for simultaneous formation of diffusion break, gate cut, and independent N and P gates for 3D transistor devices
    5.
    发明授权
    Apparatus and method for simultaneous formation of diffusion break, gate cut, and independent N and P gates for 3D transistor devices 有权

    公开(公告)号：US11574845B2

    公开(公告)日：2023-02-07

    申请号：US16848638

    申请日：2020-04-14

    Applicant: TOKYO ELECTRON LIMITED

    Inventor： Daniel Chanemougame ,  Lars Liebmann ,  Jeffrey Smith ,  Anton deVilliers

    IPC: H01L21/8238 ,  H01L27/092

    Abstract: A method of manufacturing a 3D semiconductor device, the method including forming a first target structure, the first target structure including at least one upper gate, at least one bottom gate, and a dielectric separation layer disposed between and separating the at least one upper gate and the at least one bottom gate; removing material in a plurality of material removal areas in the first target structure, the plurality of material removal areas including at least one material removal area that extends through the at least one upper gate to a top of the dielectric separation layer; and forming a first contact establishing a first electrical connection to the upper gate and a second contact establishing a second electrical connection to the at least one bottom gate, such that the first contact and second contact are independent of each other.

    Method of manufacturing a semiconductor apparatus having stacked devices
    6.
    发明申请
    Method of manufacturing a semiconductor apparatus having stacked devices 有权

    公开(公告)号：US20230024975A1

    公开(公告)日：2023-01-26

    申请号：US17954953

    申请日：2022-09-28

    Applicant: Tokyo Electron Limited

    Inventor： Lars Liebmann ,  Jeffrey Smith ,  Anton deVilliers

    IPC: H01L23/528 ,  H01L27/092 ,  H01L21/768 ,  H01L25/07

    Abstract: A method for forming a semiconductor apparatus includes forming a plurality of repetitive initial structures over a substrate of the semiconductor apparatus. An initial structure in the plurality of repetitive initial structures is formed by forming a first stack of transistors along a Z direction substantially perpendicular to a substrate plane, and forming local interconnect structures. Each of the transistors in the first stack of transistors is sandwiched between two of the local interconnect structures. Vertical conductive structures are formed substantially parallel to the Z direction, a height of one of the vertical conductive structures along the Z direction being at least a height of the initial structure. The initial structure is functionalized into a final structure by forming one or more connections each electrically coupling one of the local interconnect structures to one of the vertical conductive structures.

    Stacked three-dimensional field-effect transistors
    7.
    发明授权
    Stacked three-dimensional field-effect transistors 有权

    公开(公告)号：US11532708B2

    公开(公告)日：2022-12-20

    申请号：US17334422

    申请日：2021-05-28

    Applicant: Tokyo Electron Limited

    Inventor： Lars Liebmann ,  Jeffrey Smith ,  Daniel Chanemougame ,  Paul Gutwin

    IPC: H01L29/10 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66

    Abstract: A semiconductor device includes a first field-effect transistor positioned over a substrate, a second field-effect transistor stacked over the first field-effect transistor, a third field-effect transistor stacked over the second field-effect transistor, and a fourth field-effect transistor stacked over the third field-effect transistor. A bottom gate structure is disposed around a first channel structure of the first field-effect transistor and positioned over the substrate. An intermediate gate structure is disposed over the bottom gate structure and around a second channel structure of the second field-effect transistor and a third channel structure of the third field-effect transistor. A top gate structure is disposed over the intermediate gate structure and around a fourth channel structure of the fourth field-effect transistor. An inter-level contact is formed to bypass the intermediate gate structure from a first side of the intermediate gate structure, and arranged between the bottom gate structure and the top gate structure.

    HIGH DENSITY LOGIC FORMATION USING MULTI-DIMENSIONAL LASER ANNEALING
    9.
    发明申请
    HIGH DENSITY LOGIC FORMATION USING MULTI-DIMENSIONAL LASER ANNEALING 有权

    公开(公告)号：US20220277957A1

    公开(公告)日：2022-09-01

    申请号：US17632212

    申请日：2020-07-29

    Applicant: Tokyo Electron Limited

    Inventor： H. Jim Fulford ,  Mark I. Gardner ,  Jeffrey Smith ,  Lars Liebmann ,  Daniel Chanemougame

    IPC: H01L21/02

    Abstract: A method of forming transistor devices is described that includes forming a first transistor plane on a substrate, the first transistor plane including at least one layer of epitaxial film adaptable for forming channels of field effect transistors, depositing a first insulator layer on the first transistor plane, depositing a first layer of polycrystalline silicon on the first insulator layer, annealing the first layer of polycrystalline silicon using laser heating. The laser heating increases grain size of the first layer of polycrystalline silicon. The method further includes forming a second transistor plane on the first layer of polycrystalline silicon, the second transistor plane being adaptable for forming channels of field effect transistors, depositing a second insulator layer on the second transistor plane, depositing a second layer of polycrystalline silicon on the second insulator layer, and annealing the second layer of polycrystalline silicon using laser heating.

    Self-aligned contacts for 3D logic and memory
    10.
    发明授权
    Self-aligned contacts for 3D logic and memory 有权

    公开(公告)号：US11335599B2

    公开(公告)日：2022-05-17

    申请号：US16721583

    申请日：2019-12-19

    Applicant: Tokyo Electron Limited

    Inventor： Lars Liebmann ,  Jeffrey Smith ,  Anton J. deVilliers ,  Kandabara Tapily

    IPC: H01L21/768 ,  H01L23/522 ,  H01L27/118 ,  H01L21/8238 ,  H01L21/822 ,  H01L27/11

    Abstract: A semiconductor device includes dielectric layers and local interconnects that are stacked over a substrate alternatively, and extend along a top surface of the substrate laterally. Sidewalls of the dielectric layers and sidewalls of the local interconnects have a staircase configuration. The local interconnects are spaced apart from each other by dielectric layers and have uncovered portions by the dielectric layers. The semiconductor device also includes conductive layers selectively positioned over the uncovered portions of the local interconnects, where sidewalls of the conductive layers and sidewalls of the local interconnects are coplanar. The semiconductor device further includes isolation caps that extend from the dielectric layers. The isolation caps are positioned along sidewalls of the conductive layers and sidewalls of the local interconnects so as to separate the conductive layers from one another.

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