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公开(公告)号：US11830852B2
公开(公告)日：2023-11-28
申请号：US17541581
申请日：2021-12-03
发明人： Lars Liebmann , Jeffrey Smith , Daniel Chanemougame , Paul Gutwin , Brian Cline , Xiaoqing Xu , David Pietromonaco
IPC分类号： H01L25/00 , H01L25/065 , H01L25/18 , H01L23/528
CPC分类号： H01L25/0657 , H01L25/50 , H01L23/5286 , H01L25/18 , H01L2225/06544
摘要： Aspects of the present disclosure provide a multi-tier semiconductor structure. For example, the multi-tier semiconductor structure can include a first power delivery network (PDN) structure, and a first semiconductor device tier disposed over and electrically connected to the first PDN structure. The multi-tier semiconductor structure can further include a signal wiring tier disposed over and electrically connected to the first semiconductor device tier, a second semiconductor device tier disposed over and electrically connected to the signal wiring tier, and a second PDN structure disposed over and electrically connected to the second semiconductor device tier. The multi-tier semiconductor structure can further include a through-silicon via (TSV) structure electrically connected to the signal wiring tier, wherein the TSV structure penetrates the second PDN structure.
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公开(公告)号：US11723187B2
公开(公告)日：2023-08-08
申请号：US17644982
申请日：2021-12-17
发明人： Paul Gutwin , Lars Liebmann , Daniel Chanemougame
IPC分类号： H10B12/00 , G11C11/402 , G11C11/412 , H10B10/00
CPC分类号： H10B12/30 , G11C11/4023 , G11C11/412 , H10B10/12 , H10B12/02
摘要： In a semiconductor device, a first stack is positioned over substrate and includes a first pair of transistors and a second pair of transistors stacked over the substrate. A second stack is positioned over the substrate and adjacent to the first stack. The second stack includes a third pair of transistors and a fourth pair of transistors stacked over the substrate. A first capacitor is stacked with the first and second stacks. A second capacitor is positioned adjacent to the first capacitor and stacked with the first and second stacks. A first group of the transistors in the first and second stacks is coupled to each other to form a static random-access memory cell. A second group of the transistors in the first and second stacks is coupled to the first and second capacitors to form a first dynamic random-access memory (DRAM) cell and a second DRAM cell.
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公开(公告)号：US11574845B2
公开(公告)日：2023-02-07
申请号：US16848638
申请日：2020-04-14
IPC分类号： H01L21/8238 , H01L27/092
摘要： A method of manufacturing a 3D semiconductor device, the method including forming a first target structure, the first target structure including at least one upper gate, at least one bottom gate, and a dielectric separation layer disposed between and separating the at least one upper gate and the at least one bottom gate; removing material in a plurality of material removal areas in the first target structure, the plurality of material removal areas including at least one material removal area that extends through the at least one upper gate to a top of the dielectric separation layer; and forming a first contact establishing a first electrical connection to the upper gate and a second contact establishing a second electrical connection to the at least one bottom gate, such that the first contact and second contact are independent of each other.
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公开(公告)号：US11532708B2
公开(公告)日：2022-12-20
申请号：US17334422
申请日：2021-05-28
发明人： Lars Liebmann , Jeffrey Smith , Daniel Chanemougame , Paul Gutwin
摘要： A semiconductor device includes a first field-effect transistor positioned over a substrate, a second field-effect transistor stacked over the first field-effect transistor, a third field-effect transistor stacked over the second field-effect transistor, and a fourth field-effect transistor stacked over the third field-effect transistor. A bottom gate structure is disposed around a first channel structure of the first field-effect transistor and positioned over the substrate. An intermediate gate structure is disposed over the bottom gate structure and around a second channel structure of the second field-effect transistor and a third channel structure of the third field-effect transistor. A top gate structure is disposed over the intermediate gate structure and around a fourth channel structure of the fourth field-effect transistor. An inter-level contact is formed to bypass the intermediate gate structure from a first side of the intermediate gate structure, and arranged between the bottom gate structure and the top gate structure.
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公开(公告)号：US11488947B2
公开(公告)日：2022-11-01
申请号：US16847001
申请日：2020-04-13
摘要： An integrated circuit includes an array of unit cells, each unit cell of which including field effect transistors arranged in a stack. Local interconnect structures form select conductive paths between select terminals of the field effect transistors to define cell circuitry that is confined within each unit cell. An array of contacts is disposed on an accessible surface of the unit cell, where each contact is electrically coupled to a corresponding electrical node of the cell circuitry.
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公开(公告)号：US20220277957A1
公开(公告)日：2022-09-01
申请号：US17632212
申请日：2020-07-29
IPC分类号： H01L21/02
摘要： A method of forming transistor devices is described that includes forming a first transistor plane on a substrate, the first transistor plane including at least one layer of epitaxial film adaptable for forming channels of field effect transistors, depositing a first insulator layer on the first transistor plane, depositing a first layer of polycrystalline silicon on the first insulator layer, annealing the first layer of polycrystalline silicon using laser heating. The laser heating increases grain size of the first layer of polycrystalline silicon. The method further includes forming a second transistor plane on the first layer of polycrystalline silicon, the second transistor plane being adaptable for forming channels of field effect transistors, depositing a second insulator layer on the second transistor plane, depositing a second layer of polycrystalline silicon on the second insulator layer, and annealing the second layer of polycrystalline silicon using laser heating.
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公开(公告)号：US11114346B2
公开(公告)日：2021-09-07
申请号：US16705485
申请日：2019-12-06
IPC分类号： H01L21/8238 , H01L21/822 , H01L21/02 , H01L29/786 , H01L29/66 , H01L27/092
摘要： A method of forming transistor devices is described that includes forming a first transistor plane on a substrate, the first transistor plane including at least one layer of epitaxial film adaptable for forming channels of field effect transistors, depositing a first insulator layer on the first transistor plane, depositing a first layer of polycrystalline silicon on the first insulator layer, annealing the first layer of polycrystalline silicon using laser heating. The laser heating increases grain size of the first layer of polycrystalline silicon. The method further includes forming a second transistor plane on the first layer of polycrystalline silicon, the second transistor plane being adaptable for forming channels of field effect transistors, depositing a second insulator layer on the second transistor plane, depositing a second layer of polycrystalline silicon on the second insulator layer, and annealing the second layer of polycrystalline silicon using laser heating.
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公开(公告)号：US20200381430A1
公开(公告)日：2020-12-03
申请号：US16849630
申请日：2020-04-15
IPC分类号： H01L27/092 , H01L23/528 , H01L23/535 , H01L29/08 , H03K19/21
摘要： A 3D IC includes a substrate having a substrate surface, a first stack of semiconductor devices stacked along a thickness direction of the substrate, and a second stack of semiconductor devices stacked along the thickness direction of the substrate and provided adjacent to the first stack in a direction along the substrate surface. Each semiconductor device of the first and second stack includes a gate and a pair of source-drain regions provided on opposite sides of the respective gate, and each gate of the first and second stack is a split gate. A gate contact is physically connected to a first split gate of a first one of the semiconductor devices. The gate contact forms at least part of a local interconnect structure that electrically connects the first semiconductor device to a second semiconductor device in the 3D IC.
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公开(公告)号：US11791271B2
公开(公告)日：2023-10-17
申请号：US17306331
申请日：2021-05-03
IPC分类号： H01L23/538 , H01L21/48 , H01L27/092
CPC分类号： H01L23/5383 , H01L21/4885 , H01L27/0924
摘要： An additional set of interconnects is created in bulk material, allowing connections to active devices to be made from both above and below. The interconnects below the active devices can form a power distribution network, and the interconnects above the active devices can form a signaling network. Various accommodations can be made to suit different applications, such as encapsulating buried elements, using sacrificial material, and replacing the bulk material with a dielectric. Epitaxial material can be used throughout the formation process, allowing for the creation of a monolithic substrate.
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公开(公告)号：US11735525B2
公开(公告)日：2023-08-22
申请号：US16659251
申请日：2019-10-21
IPC分类号： H01L23/528 , H01L21/768 , H01L23/522
CPC分类号： H01L23/5286 , H01L21/76877 , H01L21/76895 , H01L23/5226 , H01L23/5283
摘要： A semiconductor device includes a first power rail, a first power input structure, a circuit and a first middle-of-line rail. The first power rail is formed in a first rail opening within a first isolation trench on a substrate. The first power input structure is configured to connect with a first terminal of a power source that is external of the semiconductor device to receive electrical power from the power source. The circuit is formed, on the substrate, by layers between the first power rail and the first power input structure. The first middle-of-line rail is formed by one or more of the layers that form the circuit. The first middle-of-line rail is configured to deliver the electrical power from the first power input structure to the first power rail, and the first power rail provides the electrical power to the circuit for operation.
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