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12 条记录 (耗时 0.013 秒)

    Integrated high efficiency gate on gate cooling
    2.
    发明授权
    Integrated high efficiency gate on gate cooling 有权

    公开(公告)号：US11581242B2

    公开(公告)日：2023-02-14

    申请号：US17344259

    申请日：2021-06-10

    申请人： Tokyo Electron Limited

    发明人： Daniel Chanemougame ,  Lars Liebmann ,  Jeffrey Smith ,  Paul Gutwin

    IPC分类号： H01L23/473 ,  H01L25/00 ,  H01L25/065 ,  H01L23/00 ,  H01L25/18

    摘要： A microfabrication device is provided. The microfabrication device includes a combined substrate including a first substrate connected to a second substrate, the first substrate having first devices and the second substrate having second devices; fluidic passages formed at a connection point between the first substrate and the second substrate, the connection point including a wiring structure that electrically connects first devices to second devices and physically connects the first substrate to the second substrate; dielectric fluid added to the fluidic passages; and a circulating mechanism configured to circulate the dielectric fluid through the fluidic passages to transfer heat.

    Three-dimensional memory cell structure
    4.
    发明授权
    Three-dimensional memory cell structure 有权

    公开(公告)号：US11723187B2

    公开(公告)日：2023-08-08

    申请号：US17644982

    申请日：2021-12-17

    申请人： Tokyo Electron Limited

    发明人： Paul Gutwin ,  Lars Liebmann ,  Daniel Chanemougame

    IPC分类号： H10B12/00 ,  G11C11/402 ,  G11C11/412 ,  H10B10/00

    CPC分类号： H10B12/30 ,  G11C11/4023 ,  G11C11/412 ,  H10B10/12 ,  H10B12/02

    摘要： In a semiconductor device, a first stack is positioned over substrate and includes a first pair of transistors and a second pair of transistors stacked over the substrate. A second stack is positioned over the substrate and adjacent to the first stack. The second stack includes a third pair of transistors and a fourth pair of transistors stacked over the substrate. A first capacitor is stacked with the first and second stacks. A second capacitor is positioned adjacent to the first capacitor and stacked with the first and second stacks. A first group of the transistors in the first and second stacks is coupled to each other to form a static random-access memory cell. A second group of the transistors in the first and second stacks is coupled to the first and second capacitors to form a first dynamic random-access memory (DRAM) cell and a second DRAM cell.

    Stacked three-dimensional field-effect transistors
    5.
    发明授权
    Stacked three-dimensional field-effect transistors 有权

    公开(公告)号：US11532708B2

    公开(公告)日：2022-12-20

    申请号：US17334422

    申请日：2021-05-28

    申请人： Tokyo Electron Limited

    发明人： Lars Liebmann ,  Jeffrey Smith ,  Daniel Chanemougame ,  Paul Gutwin

    IPC分类号： H01L29/10 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66

    摘要： A semiconductor device includes a first field-effect transistor positioned over a substrate, a second field-effect transistor stacked over the first field-effect transistor, a third field-effect transistor stacked over the second field-effect transistor, and a fourth field-effect transistor stacked over the third field-effect transistor. A bottom gate structure is disposed around a first channel structure of the first field-effect transistor and positioned over the substrate. An intermediate gate structure is disposed over the bottom gate structure and around a second channel structure of the second field-effect transistor and a third channel structure of the third field-effect transistor. A top gate structure is disposed over the intermediate gate structure and around a fourth channel structure of the fourth field-effect transistor. An inter-level contact is formed to bypass the intermediate gate structure from a first side of the intermediate gate structure, and arranged between the bottom gate structure and the top gate structure.

    Three-dimensional semiconductor device
    9.
    发明授权
    Three-dimensional semiconductor device 有权

    公开(公告)号：US11764266B2

    公开(公告)日：2023-09-19

    申请号：US18074684

    申请日：2022-12-05

    申请人： Tokyo Electron Limited

    发明人： Lars Liebmann ,  Jeffrey Smith ,  Daniel Chanemougame ,  Paul Gutwin

    IPC分类号： H01L29/10 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66

    CPC分类号： H01L29/1029 ,  H01L29/0665 ,  H01L29/66818 ,  H01L29/785

    摘要： A semiconductor device includes a first field-effect transistor positioned over a substrate, a second field-effect transistor stacked over the first field-effect transistor, a third field-effect transistor stacked over the second field-effect transistor, and a fourth field-effect transistor stacked over the third field-effect transistor. A bottom gate structure is disposed around a first channel structure of the first field-effect transistor and positioned over the substrate. An intermediate gate structure is disposed over the bottom gate structure and around a second channel structure of the second field-effect transistor and a third channel structure of the third field-effect transistor. A top gate structure is disposed over the intermediate gate structure and around a fourth channel structure of the fourth field-effect transistor. An inter-level contact is formed to bypass the intermediate gate structure from a first side of the intermediate gate structure, and arranged between the bottom gate structure and the top gate structure.