公开(公告)号：US20230402338A1

公开(公告)日：2023-12-14

申请号：US18329186

申请日：2023-06-05

Applicant: Skyworks Solutions, Inc.

Inventor： Anthony James LoBianco ,  Ki Wook Lee ,  Yi Liu

IPC: H01L23/31 ,  H01L23/498 ,  H01L23/15 ,  H05K1/18 ,  H01L21/56 ,  H05K3/40

CPC classification number: H01L23/3121 ,  H01L23/49827 ,  H01L23/15 ,  H05K1/181 ,  H01L21/563 ,  H05K3/4038 ,  H05K2201/0305

Abstract: An electronic package is provided. The electronic package includes a substrate configured to receive one or more electronic modules, a first electronic module mounted to a first side of the substrate, a first mold structure extending over at least part of the first side of the substrate; and a group of electrically conductive through-mold connections provided on the first side of the substrate. The first mold structure substantially encapsulates the group of through-mold connections. The group of through-mold connections is exposed through the first mold structure. The group of through-mold connections is configured to couple to a circuit board by a corresponding group of intermediate solder portions. The through-mold connections can have a melting point in excess of a melting point of the intermediate solder portion. Related electronic assemblies, electronic devices, and methods of manufacturing and/or mounting an electronic package are provided.

公开(公告)号：US20230343671A1

公开(公告)日：2023-10-26

申请号：US18126844

申请日：2023-03-27

Applicant: Proterial, Ltd.

Inventor： Teruyuki OMORI

IPC: H01L23/373 ,  H01L23/15 ,  H01L23/50

CPC classification number: H01L23/3735 ,  H01L23/15 ,  H01L23/50

Abstract: A ceramic substrate is provided with a flat plate-shaped insulating base composed of a ceramic, a first brazing material layer provided on a first main surface of the insulating base, second brazing material layer provided on a second main surface of the insulating base, a circuit plate composed of a metal and fixed through the first brazing material layer to the insulating base on a first main surface-side, and a heat dissipation plate composed of a metal and fixed through the second brazing material layer to the insulating base on a second main surface-side. A thickness of one of the heat dissipation plate and the circuit plate is larger than a thickness of the other. When the thickness of the heat dissipation plate is larger than the thickness of the circuit plate, a thickness of the first brazing material layer is larger than a thickness of the second brazing material layer. When the thickness of the circuit plate is larger than the thickness of the heat dissipation plate, the thickness of the second brazing material layer is larger than the thickness of the first brazing material layer.

公开(公告)号：US11784459B2

公开(公告)日：2023-10-10

申请号：US17539882

申请日：2021-12-01

Applicant: KYOCERA Corporation

Inventor： Sentarou Yamamoto ,  Youji Furukubo ,  Masanori Okamoto ,  Toshifumi Higashi

IPC: H01S5/02315 ,  H01L23/13 ,  H01S5/022 ,  H01L23/12 ,  H01L23/36 ,  H01S5/023 ,  H01S5/0233 ,  H01S5/0235 ,  H01L23/15 ,  H01L23/498 ,  H01S5/024 ,  H01S5/40 ,  H01S5/02345

CPC classification number: H01S5/02315 ,  H01L23/12 ,  H01L23/13 ,  H01L23/15 ,  H01L23/36 ,  H01L23/49827 ,  H01L23/49838 ,  H01S5/022 ,  H01S5/023 ,  H01S5/0233 ,  H01S5/0235 ,  H01S5/02469 ,  H01S5/4093 ,  H01L2224/48091 ,  H01L2924/15192 ,  H01S5/02345 ,  H01L2224/48091 ,  H01L2924/00014

Abstract: A light emitting element mounting package includes a plate-like substrate and a base that protrudes from a front surface of the substrate and has a mounting surface on which a light emitting element is mounted. A power supply terminal is provided on the front surface of the substrate, and the power supply terminal is arranged in a direction that is opposite to a direction where an emitting surface of the light emitting element is oriented. The light emitting element mounting package further includes a wiring conductor inside the substrate, wherein the wiring conductor extends to a side of the power supply terminal where one end thereof is positioned at a side of the power supply terminal with respect to the emitting surface of the light emitting element and the other end thereof is electrically connected to the power supply terminal.

公开(公告)号：US20230317620A1

公开(公告)日：2023-10-05

申请号：US17708746

申请日：2022-03-30

Applicant: Intel Corporation

Inventor： Carlton Hanna ,  Georg Seidemann ,  Eduardo De Mesa ,  Abdallah Bacha ,  Lizabeth Keser

IPC: H01L23/538 ,  H01L23/15 ,  H01L25/065 ,  H01L21/48

CPC classification number: H01L23/5383 ,  H01L23/15 ,  H01L24/16 ,  H01L21/4857 ,  H01L25/0655

Abstract: Various embodiments disclosed relate to a semiconductor assembly having a ceramic or glass interposer for connecting dies within a semiconductor package. The present disclosure includes a ceramic or glass interposer having a carrier layer of substantially glass or ceramic material and a connecting layer having at least one dielectric layer and electrical routing therein.

公开(公告)号：US11756799B1

公开(公告)日：2023-09-12

申请号：US17165825

申请日：2021-02-02

Applicant: HRL Laboratories, LLC

Inventor： Tobias Schaedler ,  Kayleigh Porter ,  Phuong Bui

IPC: H01L23/15 ,  H01L23/498 ,  H01L23/13 ,  H01L21/48

CPC classification number: H01L21/4807 ,  H01L21/4857 ,  H01L21/4867 ,  H01L23/15 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/13 ,  H01L23/49866 ,  H01L23/49883

Abstract: A ceramic article. In some embodiments, the ceramic article includes a ceramic body composed of a ceramic material; and a first conductive trace, the first conductive trace having a first portion entirely within the ceramic material, the first portion having a length of 0.5 mm and transverse dimensions less than 500 microns, the ceramic material including a plurality of ceramic particles in a ceramic matrix.

公开(公告)号：US11749574B2

公开(公告)日：2023-09-05

申请号：US17388521

申请日：2021-07-29

Applicant: Nippon Electric Glass Co., Ltd.

Inventor： Hiroki Katayama

IPC: H01L23/15 ,  H01L23/00 ,  H01L23/12 ,  H01L21/56 ,  C03C3/093 ,  C03C3/091 ,  B32B17/06 ,  C03C19/00 ,  B24B37/07

CPC classification number: H01L23/15 ,  B24B37/07 ,  B32B17/06 ,  C03C3/091 ,  C03C3/093 ,  C03C19/00 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L23/12 ,  H01L24/19 ,  H01L24/96 ,  B32B2307/538 ,  B32B2457/14 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2924/3511

Abstract: Devised are a supporting substrate capable of contributing to an increase in density of a semiconductor package and a laminate using the supporting substrate. A supporting glass substrate of the present invention includes a polished surface on a surface thereof and has a total thickness variation of less than 2.0 μm.

公开(公告)号：US11710691B2

公开(公告)日：2023-07-25

申请号：US17082512

申请日：2020-10-28

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Francis J. Carney ,  Jefferson W. Hall ,  Michael J. Seddon

IPC: H01L23/498 ,  H01L23/495 ,  H01L21/48 ,  H01L23/00 ,  H01L21/3065 ,  H01L21/78 ,  H01L21/67 ,  H01L21/66 ,  H01L21/56 ,  H01L23/31 ,  H02M3/158 ,  H01L23/482 ,  H01L25/065 ,  H01L25/00 ,  H01L23/544 ,  H01L21/02 ,  H01L21/304 ,  H01L21/308 ,  H01L27/146 ,  H01L21/288 ,  H01L21/683 ,  H01L21/768 ,  H01L23/48 ,  H01L27/02 ,  H01L27/088 ,  H01L27/14 ,  H01L29/08 ,  H01L23/15 ,  H01L23/367 ,  H01L23/14

CPC classification number: H01L23/49827 ,  H01L21/02035 ,  H01L21/288 ,  H01L21/304 ,  H01L21/308 ,  H01L21/3065 ,  H01L21/3083 ,  H01L21/486 ,  H01L21/4825 ,  H01L21/4853 ,  H01L21/565 ,  H01L21/67069 ,  H01L21/6835 ,  H01L21/76877 ,  H01L21/76898 ,  H01L21/78 ,  H01L22/12 ,  H01L22/26 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/4822 ,  H01L23/4951 ,  H01L23/49503 ,  H01L23/49541 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/49811 ,  H01L23/49838 ,  H01L23/49866 ,  H01L23/544 ,  H01L23/562 ,  H01L24/00 ,  H01L24/05 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/14 ,  H01L27/14683 ,  H01L29/0847 ,  H02M3/158 ,  H01L23/147 ,  H01L23/15 ,  H01L23/3677 ,  H01L23/49816 ,  H01L27/14625 ,  H01L27/14685 ,  H01L2221/68327 ,  H01L2223/5446 ,  H01L2223/54426 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05083 ,  H01L2224/05084 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05172 ,  H01L2224/05184 ,  H01L2224/13025 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2225/06555 ,  H01L2225/06593 ,  H01L2225/06596 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/3511 ,  H01L2924/3511 ,  H01L2924/00

Abstract: A semiconductor device has a first semiconductor die and second semiconductor die with a conductive layer formed over the first semiconductor die and second semiconductor die. The second semiconductor die is disposed adjacent to the first semiconductor die with a side surface and the conductive layer of the first semiconductor die contacting a side surface and the conductive layer of the second semiconductor die. An interconnect, such as a conductive material, is formed across a junction between the conductive layers of the first and second semiconductor die. The conductive layer may extend down the side surface of the first semiconductor die and further down the side surface of the second semiconductor die. An extension of the side surface of the first semiconductor die can interlock with a recess of the side surface of the second semiconductor die. The conductive layer extends over the extension and into the recess.

公开(公告)号：US11694966B2

公开(公告)日：2023-07-04

申请号：US17546082

申请日：2021-12-09

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Kuo-Lung Pan ,  Hao-Yi Tsai ,  Tin-Hao Kuo

IPC: H01L23/538 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L21/48 ,  H01L23/29 ,  H01L23/48 ,  H01L23/15 ,  H01L23/28 ,  H01L23/522 ,  H01L23/14 ,  H01L23/528

CPC classification number: H01L23/5389 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/568 ,  H01L23/147 ,  H01L23/15 ,  H01L23/28 ,  H01L23/293 ,  H01L23/31 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/522 ,  H01L23/528 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/562 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/214 ,  H01L2924/3511 ,  H01L2924/35121

Abstract: A chip package including a first semiconductor die, a support structure and a second semiconductor die is provided. The first semiconductor die includes a first dielectric layer and a plurality of conductive vias, the first dielectric layer includes a first region and a second region, the conductive vias is embedded in the first region of the first dielectric layer; a plurality of conductive pillars is disposed on and electrically connected to the conductive vias. The second semiconductor die is stacked over the support structure and the second region of the first dielectric layer; and an insulating encapsulant encapsulates the first semiconductor die, the second semiconductor die, the support structure and the conductive pillars, wherein the second semiconductor die is electrically connected to the first semiconductor die through the conductive pillars.

公开(公告)号：US20230209727A1

公开(公告)日：2023-06-29

申请号：US17735382

申请日：2022-05-03

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Chang Ho SEO ,  Sung Kwon AN

IPC: H05K3/46 ,  H05K1/03 ,  H05K3/00 ,  H01L23/15

CPC classification number: H05K3/4629 ,  H01L23/15 ,  H05K1/0306 ,  H05K3/0029

Abstract: A method for manufacturing a ceramic electronic component includes: forming a ceramic laminate by stacking ceramic green sheets on which internal electrode patterns are formed; obtaining an image of an upper portion of the ceramic laminate; determining cutting regions based on the image; and cutting the ceramic laminate by irradiating the cutting regions with a laser.

公开(公告)号：US20230207406A1

公开(公告)日：2023-06-29

申请号：US17561730

申请日：2021-12-24

Applicant: Intel Corporation

Inventor： Arghya SAIN ,  Andrew P. COLLINS ,  Sivaseetharaman PANDI ,  Jianyong XIE ,  Telesphor KAMGAING

IPC: H01L23/15 ,  H01L23/498 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L23/15 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2924/15311

Abstract: Embodiments disclosed herein include a package core. In an embodiment, the package core includes a first layer, where the first layer comprises glass. In an embodiment, a second layer is over the first layer, where the second layer comprises glass. In an embodiment, a third layer is over the second layer, where the third layer comprises glass. In an embodiment, a first trace is between the first layer and the second layer. In an embodiment, a second trace is between the second layer and the third layer.