公开(公告)号：US20240145413A1

公开(公告)日：2024-05-02

申请号：US18244443

申请日：2023-09-11

Applicant: Sumitomo Electric Device Innovations, Inc.

Inventor： Makoto NISHIHARA

IPC: H01L23/66 ,  H01L21/8252 ,  H01L23/00 ,  H01L23/495 ,  H01L25/16 ,  H01L27/06

CPC classification number: H01L23/66 ,  H01L21/8252 ,  H01L23/49589 ,  H01L24/05 ,  H01L24/06 ,  H01L24/32 ,  H01L24/33 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/165 ,  H01L27/0688 ,  H01L2223/6655 ,  H01L2224/05541 ,  H01L2224/05553 ,  H01L2224/05558 ,  H01L2224/05644 ,  H01L2224/0603 ,  H01L2224/06181 ,  H01L2224/32245 ,  H01L2224/32265 ,  H01L2224/3303 ,  H01L2224/33181 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48101 ,  H01L2224/48106 ,  H01L2224/4813 ,  H01L2224/48175 ,  H01L2224/48195 ,  H01L2224/48265 ,  H01L2224/49052 ,  H01L2224/49109 ,  H01L2224/49111 ,  H01L2224/49113 ,  H01L2224/49175 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2924/10253 ,  H01L2924/10254 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/10336 ,  H01L2924/10337 ,  H01L2924/10344 ,  H01L2924/10346 ,  H01L2924/13064 ,  H01L2924/19041 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/30107

Abstract: A semiconductor device includes a semiconductor chip including a substrate, a transistor provided on an upper surface of the substrate and having an input electrode to which a high frequency signal is input, an output electrode from which the high frequency signal is output, and a reference potential electrode to which a reference potential is supplied, and a metal pattern provided on the upper surface of the substrate and electrically connected to the reference potential electrode, a first capacitor including a first lower electrode provided on the metal pattern and electrically connected to the metal pattern, a first dielectric layer provided on the first lower electrode, and a first upper electrode provided on the first dielectric layer, and a first bonding wire electrically connecting the first upper electrode and a first electrode which is any one of the input electrode and the output electrode.

公开(公告)号：US11854926B2

公开(公告)日：2023-12-26

申请号：US17481459

申请日：2021-09-22

Applicant: Infineon Technologies AG

Inventor： Jens Peter Konrath ,  Christian Hecht ,  Roland Rupp ,  Andre Kabakow

IPC: H01L23/31 ,  H01L29/739 ,  H01L29/78 ,  H01L29/808 ,  H01L29/861 ,  H01L29/06 ,  H01L29/10 ,  H01L21/02 ,  H01L21/28 ,  H01L21/283 ,  H01L21/308 ,  H01L21/56 ,  H01L23/29 ,  H01L27/06 ,  H01L29/47 ,  H01L29/66 ,  H01L29/70 ,  H01L29/872 ,  H01L29/423

CPC classification number: H01L23/3171 ,  H01L21/0217 ,  H01L21/02126 ,  H01L21/02129 ,  H01L21/02164 ,  H01L21/283 ,  H01L21/28247 ,  H01L21/3081 ,  H01L21/56 ,  H01L23/29 ,  H01L23/3192 ,  H01L27/0629 ,  H01L29/0619 ,  H01L29/1066 ,  H01L29/47 ,  H01L29/66674 ,  H01L29/66901 ,  H01L29/70 ,  H01L29/7397 ,  H01L29/7801 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/808 ,  H01L29/8083 ,  H01L29/8611 ,  H01L29/872 ,  H01L29/0615 ,  H01L29/0638 ,  H01L29/0661 ,  H01L29/4236 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2924/1033 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/10331 ,  H01L2924/10335 ,  H01L2924/10346 ,  H01L2924/10373 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/13055 ,  H01L2924/00

Abstract: A semiconductor device includes a semiconductor body comprising a first surface and an edge surface, a contact electrode formed on the first surface and comprising an outer edge side, and a passivation layer section conformally covering the outer edge side of the contact electrode. The passivation layer section is a multi-layer stack comprising a first layer, a second layer, and a third layer. Each of the first, second and third layers include outer edge sides facing the edge surface and opposite facing inner edge sides. The outer edge side of the contact electrode is disposed laterally between the inner edge sides and the outer edge sides of each layer.

公开(公告)号：US20180315843A1

公开(公告)日：2018-11-01

申请号：US16029505

申请日：2018-07-06

Applicant: Transphorm Inc.

Inventor： Rakesh K. Lal

IPC: H01L29/778 ,  H01L29/423 ,  H01L21/8252 ,  H01L29/78 ,  H01L29/66 ,  H01L23/535 ,  H01L29/417 ,  H01L27/06 ,  H01L27/085 ,  H01L27/088 ,  H01L29/20 ,  H01L29/40 ,  H01L23/29 ,  H01L21/02 ,  H01L23/31 ,  H01L23/00 ,  H01L29/51

CPC classification number: H01L29/7787 ,  H01L21/0217 ,  H01L21/0254 ,  H01L21/8252 ,  H01L23/291 ,  H01L23/3171 ,  H01L23/535 ,  H01L24/48 ,  H01L27/0605 ,  H01L27/0629 ,  H01L27/085 ,  H01L27/0883 ,  H01L29/0619 ,  H01L29/0847 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/404 ,  H01L29/407 ,  H01L29/4175 ,  H01L29/4236 ,  H01L29/518 ,  H01L29/66462 ,  H01L29/66522 ,  H01L29/78 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2924/00014 ,  H01L2924/10323 ,  H01L2924/1033 ,  H01L2924/10344 ,  H01L2924/10346 ,  H01L2924/13055 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2224/45099

Abstract: A III-N enhancement-mode transistor includes a III-N structure including a conductive channel, source and drain contacts, and a gate electrode between the source and drain contacts. An insulator layer is over the III-N structure, with a recess formed through the insulator layer in a gate region of the transistor, with the gate electrode at least partially in the recess. The transistor further includes a field plate having a portion between the gate electrode and the drain contact, the field plate being electrically connected to the source contact. The gate electrode includes an extending portion that is outside the recess and extends towards the drain contact. The separation between the conductive channel and the extending portion of the gate electrode is greater than the separation between the conductive channel and the portion of the field plate that is between the gate electrode and the drain contact.

公开(公告)号：US09967937B2

公开(公告)日：2018-05-08

申请号：US15031963

申请日：2014-10-24

Applicant: Commissariat a l'energie atomique et aux energies alternatives

Inventor： Ivan-Christophe Robin ,  Hubert Bono

IPC: H01L33/00 ,  H05B33/08 ,  H01L31/18 ,  H01L31/0304 ,  H01L33/06 ,  H01L33/32 ,  H05B37/02 ,  H01L25/16 ,  H01L33/18 ,  H01L33/24

CPC classification number: H05B33/0848 ,  H01L25/167 ,  H01L31/03048 ,  H01L31/1848 ,  H01L33/0075 ,  H01L33/06 ,  H01L33/18 ,  H01L33/24 ,  H01L33/32 ,  H01L2924/0002 ,  H01L2924/10346 ,  H05B33/0815 ,  H05B33/0866 ,  H05B37/0227 ,  H01L2924/00

Abstract: A light-emitting device including a light-emitting diode including an n-doped InGaN layer and a p-doped GaN layer, and an active zone including a number m of InGaN-emitting layers each one arranged between two InGaN barrier layers, of which the indium compositions of the emitting layers are different and are greater on the side of the n-doped InGaN layer than on the side of the p-doped GaN layer, and of which the indium compositions of the barrier layers are different and which are greater on the side of the n-doped InGaN layer than on the side of the p-doped GaN layer. An electric power supply supplies the diode with a periodic signal. A controller of the power supply can alter the peak value of the periodic signal according to a spectrum of the light emitted.

公开(公告)号：US20170317043A1

公开(公告)日：2017-11-02

申请号：US15654512

申请日：2017-07-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yueh-Chuan LEE ,  Chia-Chan CHEN

IPC: H01L23/00 ,  H01L23/58 ,  H01L21/306 ,  H01L21/78 ,  H01L33/00

CPC classification number: H01L24/06 ,  H01L21/30604 ,  H01L21/78 ,  H01L23/585 ,  H01L24/03 ,  H01L24/94 ,  H01L33/0095 ,  H01L2224/05016 ,  H01L2224/06179 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/10331 ,  H01L2924/10335 ,  H01L2924/10336 ,  H01L2924/10338 ,  H01L2924/10342 ,  H01L2924/10346 ,  H01L2924/2064

Abstract: The semiconductor die includes a base body, protruding portions and bonding pads. The base body has sidewalls. The protruding portions are laterally protruding from the sidewalls respectively. The bonding pads are disposed on the protruding portions respectively. The wafer dicing method includes following operations. Chips are formed on a semiconductor wafer. Bonding pads are formed at a border line between every two of the adjacent chips. A scribe line is formed and disposed along the bonding pads. A photolithographic pattern is formed on a top layer of the semiconductor wafer to expose the scribe line. The scribe line is etched to a depth in the semiconductor wafer substantially below the top layer to form an etched pattern. A back surface of the semiconductor wafer is thinned until the etched pattern in the semiconductor wafer is exposed.

公开(公告)号：US09520341B2

公开(公告)日：2016-12-13

申请号：US14663276

申请日：2015-03-19

Applicant: Infineon Technologies Americas Corp.

Inventor： Eung San Cho ,  Chuan Cheah

IPC: H01L23/495 ,  H01L25/16 ,  H01L23/00

CPC classification number: H01L23/49517 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/37 ,  H01L24/40 ,  H01L24/48 ,  H01L24/49 ,  H01L25/165 ,  H01L2224/0603 ,  H01L2224/371 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/10323 ,  H01L2924/1033 ,  H01L2924/10334 ,  H01L2924/10344 ,  H01L2924/10346 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1426 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099

Abstract: One exemplary disclosed embodiment comprises a high power semiconductor package configured as a buck converter having a control transistor and a sync transistor disposed on a common leadframe pad, a driver integrated circuit (IC) for driving the control and sync transistors, and conductive clips electrically coupling the top surfaces of the transistors to substrate pads such as leadframe pads. In this manner, the leadframe and the conductive clips provide efficient grounding or current conduction by direct mechanical connection and large surface area conduction, thereby enabling a package with significantly reduced electrical resistance, form factor, complexity, and cost when compared to conventional packaging methods using wirebonds for transistor interconnections.

Abstract translation: 一个示例性的公开的实施例包括被配置为具有控制晶体管和设置在公共引线框焊盘上的同步晶体管的降压转换器的高功率半导体封装，用于驱动控制和同步晶体管的驱动器集成电路（IC） 晶体管的顶表面到衬底焊盘，例如引线框焊盘。 以这种方式，引线框架和导电夹子通过直接机械连接和大的表面积传导提供有效的接地或电流传导，从而与使用以下的传统封装方法相比，能够实现具有显着降低的电阻，形状因素，复杂性和成本的封装 用于晶体管互连的引线。

公开(公告)号：US09111921B2

公开(公告)日：2015-08-18

申请号：US14022584

申请日：2013-09-10

Applicant: International Rectifier Corporation

Inventor： Eung San Cho ,  Andrew N. Sawle ,  Mark Pavier ,  Daniel Cutler

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L23/495 ,  H01L25/07 ,  H01L25/11 ,  H01L21/48 ,  H01L25/16 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L21/84 ,  H01L21/4825 ,  H01L21/4871 ,  H01L21/561 ,  H01L23/3121 ,  H01L23/49562 ,  H01L23/49568 ,  H01L23/49575 ,  H01L24/16 ,  H01L24/24 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L25/072 ,  H01L25/117 ,  H01L25/16 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/16245 ,  H01L2224/24137 ,  H01L2224/24245 ,  H01L2224/29101 ,  H01L2224/2929 ,  H01L2224/32245 ,  H01L2224/73259 ,  H01L2224/73267 ,  H01L2224/8382 ,  H01L2224/8384 ,  H01L2224/92224 ,  H01L2224/92244 ,  H01L2924/10253 ,  H01L2924/10323 ,  H01L2924/10325 ,  H01L2924/1033 ,  H01L2924/10334 ,  H01L2924/10341 ,  H01L2924/10344 ,  H01L2924/10346 ,  H01L2924/10355 ,  H01L2924/10356 ,  H01L2924/10357 ,  H01L2924/10358 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/1426 ,  H01L2924/1815 ,  H01L2924/00 ,  H01L2924/0665 ,  H01L2924/00014 ,  H01L2924/014

Abstract: In one implementation, a semiconductor package includes a control conductive carrier having a die side and an opposite input/output (I/O) side connecting the semiconductor package to a mounting surface. The semiconductor package also includes a control FET of a power converter switching stage having a control drain attached to the die side of the control conductive carrier. The control conductive carrier is configured to sink heat produced by the control FET into the mounting surface. The semiconductor package includes a sync conductive carrier having another die side and another opposite I/O side connecting the semiconductor package to the mounting surface, and a sync FET of the power converter switching stage having a sync source attached to the die side of the sync conductive carrier.

Abstract translation: 在一个实施方案中，半导体封装包括具有裸片侧的控制导电载体和将半导体封装连接到安装表面的相反的输入/输出（I / O）侧。 半导体封装还包括功率转换器开关级的控制FET，其具有附着到控制导电载体的管芯侧的控制漏极。 控制导电载体被配置为将由控制FET产生的热量吸收到安装表面中。 半导体封装包括具有另一管芯侧的同步导电载体和将半导体封装连接到安装表面的另一个相反的I / O侧，以及功率转换器开关级的同步FET，其具有连接到同步的管芯侧的同步源 导电载体。

公开(公告)号：US09087718B2

公开(公告)日：2015-07-21

申请号：US13799989

申请日：2013-03-13

Applicant: Transphorm Inc.

Inventor： Rakesh K. Lal

IPC: H01L29/66 ,  H01L27/088 ,  H01L29/78 ,  H01L21/8252 ,  H01L27/06 ,  H01L27/085 ,  H01L29/423

CPC classification number: H01L29/7787 ,  H01L21/0217 ,  H01L21/0254 ,  H01L21/8252 ,  H01L23/291 ,  H01L23/3171 ,  H01L23/535 ,  H01L24/48 ,  H01L27/0605 ,  H01L27/0629 ,  H01L27/085 ,  H01L27/0883 ,  H01L29/2003 ,  H01L29/404 ,  H01L29/407 ,  H01L29/4175 ,  H01L29/4236 ,  H01L29/518 ,  H01L29/66462 ,  H01L29/66522 ,  H01L29/78 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2924/00014 ,  H01L2924/10323 ,  H01L2924/1033 ,  H01L2924/10344 ,  H01L2924/10346 ,  H01L2924/13055 ,  H01L2924/13064 ,  H01L2924/00 ,  H01L2224/45099

Abstract: A III-N enhancement-mode transistor includes a III-N structure including a conductive channel, source and drain contacts, and a gate electrode between the source and drain contacts. An insulator layer is over the III-N structure, with a recess formed through the insulator layer in a gate region of the transistor, with the gate electrode at least partially in the recess. The transistor further includes a field plate having a portion between the gate electrode and the drain contact, the field plate being electrically connected to the source contact. The gate electrode includes an extending portion that is outside the recess and extends towards the drain contact. The separation between the conductive channel and the extending portion of the gate electrode is greater than the separation between the conductive channel and the portion of the field plate that is between the gate electrode and the drain contact.

Abstract translation: III-N增强型晶体管包括III-N结构，其包括导电沟道，源极和漏极接触以及源极和漏极接触之间的栅电极。 绝缘体层在III-N结构之上，在晶体管的栅极区中通过绝缘体层形成凹槽，栅电极至少部分地在凹槽中。 晶体管还包括具有在栅电极和漏极接触之间的部分的场板，场板电连接到源触点。 栅极电极包括在凹部外部并朝向漏极接触部延伸的延伸部分。 导电沟道和栅电极的延伸部分之间的间隔大于导电通道与栅电极和漏极接触之间的场板部分之间的间隔。

公开(公告)号：US20140175630A1

公开(公告)日：2014-06-26

申请号：US14192756

申请日：2014-02-27

Applicant: International Rectifier Corporation

Inventor： Eung San Cho ,  Chuan Cheah

IPC: H01L23/495

CPC classification number: H01L23/49517 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/37 ,  H01L24/40 ,  H01L24/48 ,  H01L24/49 ,  H01L25/165 ,  H01L2224/0603 ,  H01L2224/371 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/10323 ,  H01L2924/1033 ,  H01L2924/10334 ,  H01L2924/10344 ,  H01L2924/10346 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1426 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099

Abstract: One exemplary disclosed embodiment comprises a high power semiconductor package configured as a buck converter having a control transistor and a sync transistor disposed on a common leadframe pad, a driver integrated circuit (IC) for driving the control and sync transistors, and conductive clips electrically coupling the top surfaces of the transistors to substrate pads such as leadframe pads. In this manner, the leadframe and the conductive clips provide efficient grounding or current conduction by direct mechanical connection and large surface area conduction, thereby enabling a package with significantly reduced electrical resistance, form factor, complexity, and cost when compared to conventional packaging methods using wirebonds for transistor interconnections.

Abstract translation: 一个示例性的公开的实施例包括被配置为具有控制晶体管和设置在公共引线框焊盘上的同步晶体管的降压转换器的高功率半导体封装，用于驱动控制和同步晶体管的驱动器集成电路（IC） 晶体管的顶表面到衬底焊盘，例如引线框焊盘。 以这种方式，引线框架和导电夹子通过直接机械连接和大的表面积传导提供有效的接地或电流传导，从而与使用以下的传统封装方法相比，能够实现具有显着降低的电阻，形状因素，复杂性和成本的封装 用于晶体管互连的引线。

公开(公告)号：US08664754B2

公开(公告)日：2014-03-04

申请号：US13095527

申请日：2011-04-27

Applicant: Eung San Cho ,  Chuan Cheah

Inventor： Eung San Cho ,  Chuan Cheah

IPC: H01L23/495

CPC classification number: H01L23/49517 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/37 ,  H01L24/40 ,  H01L24/48 ,  H01L24/49 ,  H01L25/165 ,  H01L2224/0603 ,  H01L2224/371 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/10323 ,  H01L2924/1033 ,  H01L2924/10334 ,  H01L2924/10344 ,  H01L2924/10346 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1426 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099

Abstract: One exemplary disclosed embodiment comprises a high power semiconductor package configured as a buck converter having a control transistor and a sync transistor disposed on a common leadframe pad, a driver integrated circuit (IC) for driving the control and sync transistors, and conductive clips electrically coupling the top surfaces of the transistors to substrate pads such as leadframe pads. In this manner, the leadframe and the conductive clips provide efficient grounding or current conduction by direct mechanical connection and large surface area conduction, thereby enabling a package with significantly reduced electrical resistance, form factor, complexity, and cost when compared to conventional packaging methods using wirebonds for transistor interconnections.

Abstract translation: 一个示例性的公开的实施例包括被配置为具有控制晶体管和设置在公共引线框焊盘上的同步晶体管的降压转换器的高功率半导体封装，用于驱动控制和同步晶体管的驱动器集成电路（IC） 晶体管的顶表面到衬底焊盘，例如引线框焊盘。 以这种方式，引线框架和导电夹子通过直接机械连接和大的表面积传导提供有效的接地或电流传导，从而与使用以下的传统封装方法相比，能够实现具有显着降低的电阻，形状因素，复杂性和成本的封装 用于晶体管互连的引线。