公开(公告)号：US20170125309A1

公开(公告)日：2017-05-04

申请号：US14927816

申请日：2015-10-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yueh-Chuan LEE ,  Chia-Chan CHEN ,  Ping-Chieh CHIN

IPC: H01L21/66 ,  G01R31/28

CPC classification number: H01L22/14 ,  G01R31/2884 ,  H01L22/32 ,  H01L22/34

Abstract: Test line structures on a wafer are provided. A first testing pad is formed in a scribe line of the wafer. A second testing pad is formed in the scribe line. A transistor under test is formed in the scribe line and is coupled between the first testing pad and the second testing pad. A device is formed in the scribe line and is coupled between the first testing pad and the transistor under test. A third testing pad is formed in the scribe line and is coupled between the device and the transistor under test. A current passing through the transistor under test is measured via the second testing pad or the first testing pad when a first voltage is applied to the first testing pad, wherein the first voltage is determined according to a second voltage from the third testing pad.

公开(公告)号：US20220367538A1

公开(公告)日：2022-11-17

申请号：US17876438

申请日：2022-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yueh-Chuan LEE ,  Shih-Hsien HUANG ,  Chia-Chan CHEN ,  Pu-Fang CHEN

IPC: H01L27/146

Abstract: Apparatus and methods for effective impurity gettering are described herein. In some embodiments, a described device includes: a substrate; a pixel region disposed in the substrate; an isolation region disposed in the substrate and within a proximity of the pixel region; and a heterogeneous layer on the seed area. The isolation region comprises a seed area including a first semiconductor material. The heterogeneous layer comprises a second semiconductor material that has a lattice constant different from that of the first semiconductor material.

公开(公告)号：US20220059582A1

公开(公告)日：2022-02-24

申请号：US16998525

申请日：2020-08-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yueh-Chuan LEE ,  Shih-Hsien HUANG ,  Chia-Chan CHEN ,  Pu-Fang Chen

IPC: H01L27/146

Abstract: Apparatus and methods for effective impurity gettering are described herein. In some embodiments, a described device includes: a substrate; a pixel region disposed in the substrate; an isolation region disposed in the substrate and within a proximity of the pixel region; and a heterogeneous layer on the seed area. The isolation region comprises a seed area including a first semiconductor material. The heterogeneous layer comprises a second semiconductor material that has a lattice constant different from that of the first semiconductor material.

公开(公告)号：US20160181213A1

公开(公告)日：2016-06-23

申请号：US14577141

申请日：2014-12-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yueh-Chuan LEE ,  Chia-Chan CHEN

IPC: H01L23/00 ,  H01L21/78 ,  H01L21/306 ,  H01L23/58

CPC classification number: H01L24/06 ,  H01L21/30604 ,  H01L21/78 ,  H01L23/585 ,  H01L24/03 ,  H01L24/94 ,  H01L33/0095 ,  H01L2224/05016 ,  H01L2224/06179 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/10331 ,  H01L2924/10335 ,  H01L2924/10336 ,  H01L2924/10338 ,  H01L2924/10342 ,  H01L2924/10346 ,  H01L2924/2064

Abstract: The semiconductor die includes a base body, protruding portions and bonding pads. The base body has sidewalls. The protruding portions are laterally protruding from the sidewalls respectively. The bonding pads are disposed on the protruding portions respectively. The wafer dicing method includes following operations. Chips are formed on a semiconductor wafer. Bonding pads are formed on a border line between every two of the adjacent chips. A scribe line is formed and disposed along the bonding pads. A photolithographic pattern is formed on a top surface of the semiconductor wafer to expose the scribe line. The scribe line is etched to a depth in the semiconductor wafer substantially below the top surface layer to form an etched pattern. A back surface of the semiconductor wafer is thinned until the etched pattern in the wafer substrate is exposed.

Abstract translation: 半导体管芯包括基体，突出部分和接合焊盘。 基体具有侧壁。 突出部分分别从侧壁侧向突出。 接合焊盘分别设置在突出部分上。 晶片切割方法包括以下操作。 在半导体晶片上形成芯片。 接合焊盘形成在每两个相邻芯片之间的边界线上。 沿着焊盘形成并布置划线。 在半导体晶片的顶表面上形成光刻图案以暴露刻划线。 将划刻线蚀刻到基本上在顶表面层下方的半导体晶片的深度，以形成蚀刻图形。 半导体晶片的背面变薄，直到晶片衬底中的蚀刻图案露出。

公开(公告)号：US20170317043A1

公开(公告)日：2017-11-02

申请号：US15654512

申请日：2017-07-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yueh-Chuan LEE ,  Chia-Chan CHEN

IPC: H01L23/00 ,  H01L23/58 ,  H01L21/306 ,  H01L21/78 ,  H01L33/00

CPC classification number: H01L24/06 ,  H01L21/30604 ,  H01L21/78 ,  H01L23/585 ,  H01L24/03 ,  H01L24/94 ,  H01L33/0095 ,  H01L2224/05016 ,  H01L2224/06179 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/10331 ,  H01L2924/10335 ,  H01L2924/10336 ,  H01L2924/10338 ,  H01L2924/10342 ,  H01L2924/10346 ,  H01L2924/2064

Abstract: The semiconductor die includes a base body, protruding portions and bonding pads. The base body has sidewalls. The protruding portions are laterally protruding from the sidewalls respectively. The bonding pads are disposed on the protruding portions respectively. The wafer dicing method includes following operations. Chips are formed on a semiconductor wafer. Bonding pads are formed at a border line between every two of the adjacent chips. A scribe line is formed and disposed along the bonding pads. A photolithographic pattern is formed on a top layer of the semiconductor wafer to expose the scribe line. The scribe line is etched to a depth in the semiconductor wafer substantially below the top layer to form an etched pattern. A back surface of the semiconductor wafer is thinned until the etched pattern in the semiconductor wafer is exposed.

公开(公告)号：US20160260770A1

公开(公告)日：2016-09-08

申请号：US15153615

申请日：2016-05-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yueh-Chuan LEE

IPC: H01L27/146 ,  H01L31/18

CPC classification number: H01L27/14689 ,  H01L27/14612 ,  H01L27/1463 ,  H01L27/14643 ,  H01L27/14687 ,  H01L31/1812

Abstract: An image sensor device includes a silicon-based substrate, a silicon-germanium epitaxy layer, an isolation feature, an active pixel cell and a logic circuit. The silicon-germanium epitaxy layer is on the silicon-based substrate, in which the silicon-germanium epitaxy layer has a composition of Si1-xGex, where 0

Abstract translation: 图像传感器装置包括硅基衬底，硅 - 锗外延层，隔离特征，有源像素单元和逻辑电路。 硅 - 锗外延层位于硅基衬底上，其中硅 - 锗外延层具有Si1-xGex的组成，其中0

公开(公告)号：US20190067343A1

公开(公告)日：2019-02-28

申请号：US15690343

申请日：2017-08-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chia-Chan CHEN ,  Yueh-Chuan LEE ,  Ta-Hsin CHEN ,  Shih-Hsien HUANG ,  Chih-Huang LI

IPC: H01L27/146

CPC classification number: H01L27/1461 ,  H01L27/14612 ,  H01L27/1463 ,  H01L27/14643 ,  H01L27/14689 ,  H01L27/14698

Abstract: A photosensor device and the method of making the same are provided. In one embodiment, the device includes at least one pixel cell. The at least one pixel cell includes a substrate formed from a semiconductor material, and includes first and second photosensor regions. The first photosensor region is disposed in the substrate and includes a first dopant of a first conductivity type. The second photosensor region is disposed above the first photosensor region and includes a second dopant of a second conductivity type. The second photosensor region can have an increase in dopant concentration from an outer edge to a center portion therein.

公开(公告)号：US20180301502A1

公开(公告)日：2018-10-18

申请号：US15489019

申请日：2017-04-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yueh-Chuan LEE ,  Ta-Hsin Chen ,  Chia-Chan Chen ,  Chih-Huang Li ,  Ren-Jie Lin ,  Jung-I Lin

IPC: H01L27/146

CPC classification number: H01L27/14687 ,  H01L27/1463 ,  H01L27/14643

Abstract: A method for forming an image sensor device on a substrate is disclosed. The method includes (a) recessing a portion of the substrate thereby forming a first shallow trench; (b) forming a spacer layer surrounding at least part of a sidewall of the first shallow trench; and (c) forming a first deep trench that extends below the first shallow trench by further recessing the substrate while using the spacer layer as a mask.

公开(公告)号：US20180166475A1

公开(公告)日：2018-06-14

申请号：US15402836

申请日：2017-01-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Chan CHEN ,  Yueh-Chuan LEE ,  Chih-Huang LI ,  Ta-Hsin CHEN

IPC: H01L27/146

CPC classification number: H01L27/1463 ,  H01L27/14621 ,  H01L27/14632 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14645 ,  H01L27/14685 ,  H01L27/14687 ,  H01L27/14689

Abstract: A method for forming a backside illuminated (BSI) image sensor device structure is provided. The BSI image sensor includes a first substrate having a top surface and a bottom surface, and a plurality of pixel regions formed at the top surface of the first substrate. The BSI image sensor also includes a grid structure through the first substrate and between two adjacent pixel regions. The grid structure extends continuously through the first substrate in a vertical direction and has a top surface and a bottom surface, the top surface of the grid structure protrudes above the bottom surface of the first substrate, and the bottom surface is leveled with the top surface of the first substrate.

公开(公告)号：US20150221689A1

公开(公告)日：2015-08-06

申请号：US14170968

申请日：2014-02-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Yueh-Chuan LEE ,  Tzo-Hung LUO

IPC: H01L27/146

CPC classification number: H01L27/1461 ,  H01L27/14643 ,  H01L27/14689

Abstract: Embodiments of mechanisms for forming an image sensor device structure are provided. The image sensor device structure includes a substrate and a transfer transistor formed on the substrate. The image sensor device structure also includes a floating node formed in the substrate and a photosensitive element formed in the substrate. The transfer transistor is formed between the floating node and the photosensitive element, and the photosensitive element includes a first doping region with a lateral doping gradient.

Abstract translation: 提供了用于形成图像传感器装置结构的机构的实施例。 图像传感器装置结构包括基板和形成在基板上的转移晶体管。 图像传感器装置结构还包括形成在衬底中的浮动节点和形成在衬底中的感光元件。 传输晶体管形成在浮动节点和感光元件之间，并且光敏元件包括具有横向掺杂梯度的第一掺杂区域。