公开(公告)号：US20240321966A1

公开(公告)日：2024-09-26

申请号：US18731465

申请日：2024-06-03

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shahaji B. More

IPC: H01L29/08 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0847 ,  H01L21/823418 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858

Abstract: The present disclosure relates an integrated chip. The integrated chip may include a semiconductor substrate having sidewalls that form a first fin and a second fin. A dielectric material is arranged between the first fin and the second fin. A source/drain region is disposed on the first fin and the second fin. The source/drain region continuously extends from directly over the first fin to directly over the second fin. Fin spacers are arranged over the dielectric material and cover lower sidewalls of the source/drain region. The lower sidewalls include a first lower sidewall having a first height and a second lower sidewall that faces the first lower sidewall and that has a second height. The first height is different than the second height.

公开(公告)号：US20240321960A1

公开(公告)日：2024-09-26

申请号：US18613324

申请日：2024-03-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinchan Yun ,  Sungil Park ,  Jaehyun Park ,  Dongkyu Lee ,  Kyuman Hwang

IPC: H01L29/06 ,  H01L27/092 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/0673 ,  H01L27/092 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: A multi-stack semiconductor device includes a substrate, a device isolation layer, first channels, first gate lines covering the first channel, extending in a second horizontal direction, and spaced apart from each other in the first horizontal direction, first source/drain areas arranged on both sides of each of the first channels in the first horizontal direction, a second channel arranged apart from the first gate line in the vertical direction over any one of the first gate lines, a second gate line, second source/drain areas, a third channel arranged apart from the second gate line in the vertical direction over the second gate line, a third gate line, third source/drain areas, and a first lower source/drain contact extending in the vertical direction and connected to each of the first source/drain area, the second source/drain area, and the third source/drain area.

公开(公告)号：US12100735B2

公开(公告)日：2024-09-24

申请号：US18115913

申请日：2023-03-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Namkyu Edward Cho ,  Seung Soo Hong ,  Geum Jung Seong ,  Seung Hun Lee ,  Jeong Yun Lee

IPC: H01L29/06 ,  H01L21/02 ,  H01L21/306 ,  H01L21/311 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/092 ,  H01L29/08 ,  H01L29/165 ,  H01L29/78 ,  H10B10/00

CPC classification number: H01L29/0847 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/02636 ,  H01L21/30604 ,  H01L21/31111 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L27/0207 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/0869 ,  H01L29/165 ,  H01L29/7848 ,  H10B10/12

Abstract: A semiconductor device includes fin patterns on a substrate, at least one gate electrode intersecting the fin patterns, source/drain regions on upper surfaces of the fin patterns, and at least one blocking layer on a sidewall of a first fin pattern of the fin patterns, the at least one blocking layer extending above an upper surface of the first fin pattern of the fin patterns, wherein a first source/drain region of the source/drain regions that is on the upper surface of the first fin pattern has an asymmetric shape and is in direct contact with the at least one blocking layer.

公开(公告)号：US12100628B2

公开(公告)日：2024-09-24

申请号：US17843727

申请日：2022-06-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jhon Jhy Liaw

IPC: H01L21/8238 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L27/092 ,  H01L29/08

CPC classification number: H01L21/823871 ,  H01L21/76816 ,  H01L21/76877 ,  H01L21/823814 ,  H01L21/823821 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0924 ,  H01L29/0847

Abstract: Interconnect structures and corresponding formation techniques for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary interconnect structure for a FinFET includes a gate node via electrically coupled to a gate of the FinFET, a source node via electrically coupled to a source of the FinFET, and a drain node via electrically coupled to a drain of the FinFET. A source node via dimension ratio defines a longest dimension of the source node via relative to a shortest dimension of the source node via, and a drain node via dimension ratio defines a longest dimension of the drain node via relative to a shortest dimension of the drain node via. The source node via dimension ratio is greater than the drain node via dimension ratio. In some implementations, the source node via dimension ratio is greater than 2, and the drain node via dimension ratio is less than 1.2.

公开(公告)号：US20240313097A1

公开(公告)日：2024-09-19

申请号：US18513740

申请日：2023-11-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JUNGGIL YANG ,  TAEHYUN KIM ,  TAEWON HA

IPC: H01L29/775 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66

CPC classification number: H01L29/775 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66553

Abstract: Disclosed are a semiconductor device and a method of fabricating the same. The semiconductor device includes a substrate including a first region and a second region; an active region on the first region and a peripheral active region on the second region; a channel pattern on the active region; a peripheral channel pattern on the peripheral active region; a first gate electrode on the channel pattern; and a second gate electrode on the peripheral channel pattern. A linewidth of the second gate electrode is larger than a linewidth of the first gate electrode, and a difference in height between the first and second gate electrodes is smaller than about 10 nm, and a top surface of the second gate electrode has a doubly-concave shape.

公开(公告)号：US20240313077A1

公开(公告)日：2024-09-19

申请号：US18537536

申请日：2023-12-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chulsung KIM ,  Yeonghan GWON ,  Jinkyung SON ,  Jaepo LIM

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L29/42392 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/41733 ,  H01L29/66439 ,  H01L29/775

Abstract: Disclosed is a semiconductor device comprising a substrate including an active pattern, a channel pattern on the active pattern and including semiconductor patterns that are vertically stacked and spaced apart from each other, a source/drain pattern connected to the semiconductor patterns, a gate electrode on the semiconductor patterns and including inner electrodes between neighboring semiconductor patterns and an outer electrode on an uppermost semiconductor pattern, and a capping pattern on a top surface of the outer electrode. A line-width of the outer electrode is a first width. The outer electrode has a first height. The first height is equal to or less than the first width.

公开(公告)号：US12096629B2

公开(公告)日：2024-09-17

申请号：US18344161

申请日：2023-06-29

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hung-Ling Shih ,  Yong-Shiuan Tsair

IPC: H01L29/423 ,  G11C29/14 ,  H01L21/28 ,  H01L21/311 ,  H01L21/3213 ,  H01L23/522 ,  H01L23/528 ,  H01L29/08 ,  H01L29/66 ,  H01L29/788 ,  H10B41/30 ,  H10B41/42

CPC classification number: H10B41/42 ,  G11C29/14 ,  H01L21/31116 ,  H01L21/32137 ,  H01L23/5226 ,  H01L23/528 ,  H01L29/0847 ,  H01L29/40114 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/788 ,  H10B41/30 ,  H01L29/66545

Abstract: Various embodiments of the present application are directed to a method for forming an integrated circuit (IC) comprising forming a multilayer film to form a plurality of memory cell structures disposed over a substrate and a plurality of memory test structures next to the memory cell structures. A memory test structure comprises a dummy control gate separated from the substrate by a dummy floating gate. The method further comprises forming a conductive floating gate test contact via along sidewalls of the dummy control gate and the dummy floating gate.

公开(公告)号：US12094971B2

公开(公告)日：2024-09-17

申请号：US18310022

申请日：2023-05-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yunseong Lee ,  Jinseong Heo ,  Sangwook Kim ,  Sanghyun Jo

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/28 ,  H01L29/08 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H10B51/30

CPC classification number: H01L29/78391 ,  H01L21/02175 ,  H01L21/022 ,  H01L21/0228 ,  H01L29/0847 ,  H01L29/40111 ,  H01L29/42364 ,  H01L29/513 ,  H01L29/516 ,  H01L29/517 ,  H01L29/6684 ,  H01L21/02181 ,  H01L21/02189 ,  H10B51/30

Abstract: An electronic device includes a ferroelectric layer arranged on a channel region and a gate electrode arranged on the ferroelectric layer. The ferroelectric layer includes a plurality of first oxide monolayers and a second oxide monolayers that is arranged between the substrate and the gate electrode and include a material different from a material of the first oxide monolayers. The first oxide monolayers include oxide monolayers that are alternately formed and include materials different from one another.

公开(公告)号：US12094951B1

公开(公告)日：2024-09-17

申请号：US18136493

申请日：2023-04-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Chin Chang ,  Ming-Huan Tsai ,  Li-Te Lin ,  Pinyen Lin

IPC: H01L29/49 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/40 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/4983 ,  H01L21/823431 ,  H01L21/823475 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/7851

Abstract: A semiconductor device and methods of fabricating the same are disclosed. The method can include forming a fin structure on a substrate, forming a source/drain (S/D) region on the fin structure, forming a gate structure on the fin structure adjacent to the S/D region, and forming a capping structure on the gate structure. The forming the capping structure includes forming a conductive cap on the gate structure, forming a cap liner on the conductive cap, and forming a carbon-based cap on the cap liner. The method further includes forming a first contact structure on the S/D region, forming an insulating cap on the first contact structure, and forming a second contact structure on the conductive cap.

公开(公告)号：US12087833B2

公开(公告)日：2024-09-10

申请号：US18380754

申请日：2023-10-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Heon Bok Lee ,  Dae Yong Kim ,  Wan Don Kim ,  Jeong Hyuk Yim ,  Won Keun Chung ,  Hyo Seok Choi ,  Sang Jin Hyun

IPC: H01L29/417 ,  H01L21/768 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/41775 ,  H01L21/76897 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/6681 ,  H01L29/7851

Abstract: A semiconductor device includes an active pattern on a substrate, the active pattern extending in a first direction, a gate electrode on the active pattern, the gate electrode extending in a second direction intersecting the first direction and including a first portion and a second portion arranged along the second direction, a first contact plug on the gate electrode, the first contact plug being connected to a top surface of the second portion of the gate electrode, a source/drain region in the active pattern on a sidewall of the gate electrode, and a source/drain contact on the source/drain region, a height of a top surface of the source/drain contact being higher than a top surface of the first portion of the gate electrode and lower than the top surface of the second portion of the gate electrode.