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    Reducing pattern loading in the etch-back of metal gate
    7.
    发明授权
    Reducing pattern loading in the etch-back of metal gate 有权

    公开(公告)号：US11626506B2

    公开(公告)日：2023-04-11

    申请号：US17306316

    申请日：2021-05-03

    申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

    发明人： Po-Chin Chang ,  Wei-Hao Wu ,  Li-Te Lin ,  Pinyen Lin

    IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/49

    摘要： A method includes removing a dummy gate to leave a trench between gate spacers, forming a gate dielectric extending into the trench, depositing a metal layer over the gate dielectric, with the metal layer including a portion extending into the trench, depositing a filling region into the trench, with the metal layer have a first and a second vertical portion on opposite sides of the filling region, etching back the metal layer, with the filling region at least recessed less than the metal layer, and remaining parts of the portion of the metal layer forming a gate electrode, depositing a dielectric material into the trench, and performing a planarization to remove excess portions of the dielectric material. A portion of the dielectric material in the trench forms at least a portion of a dielectric hard mask over the gate electrode.

    CAPPING STRUCTURES IN SEMICONDUCTOR DEVICES
    8.
    发明申请
    CAPPING STRUCTURES IN SEMICONDUCTOR DEVICES 有权

    公开(公告)号：US20220344486A1

    公开(公告)日：2022-10-27

    申请号：US17238968

    申请日：2021-04-23

    申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

    发明人： Po-Chin CHANG ,  Ming-Huan Tsai ,  Li-Te Lin ,  Pinyen Lin

    IPC分类号： H01L29/49 ,  H01L29/78 ,  H01L29/08 ,  H01L29/417 ,  H01L29/40 ,  H01L29/66

    摘要： A semiconductor device and methods of fabricating the same are disclosed. The method can include forming a fin structure on a substrate, forming a source/drain (S/D) region on the fin structure, forming a gate structure on the fin structure adjacent to the S/D region, and forming a capping structure on the gate structure. The forming the capping structure includes forming a conductive cap on the gate structure, forming a cap liner on the conductive cap, and forming a carbon-based cap on the cap liner. The method further includes forming a first contact structure on the S/D region, forming an insulating cap on the first contact structure, and forming a second contact structure on the conductive cap.

    Method for FinFET fabrication and structure thereof
    9.
    发明授权
    Method for FinFET fabrication and structure thereof 有权

    公开(公告)号：US11056393B2

    公开(公告)日：2021-07-06

    申请号：US16298720

    申请日：2019-03-11

    申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

    发明人： Han-Yu Lin ,  Yi-Ruei Jhan ,  Fang-Wei Lee ,  Tze-Chung Lin ,  Chao-Hsien Huang ,  Li-Te Lin ,  Pinyen Lin ,  Akira Mineji

    IPC分类号： H01L21/8234 ,  H01L27/088 ,  H01L21/265 ,  H01L21/764 ,  H01L21/3105 ,  H01L21/02 ,  H01L21/311

    摘要： A method for FinFET fabrication includes forming at least three semiconductor fins over a substrate, wherein first, second, and third of the semiconductor fins are lengthwise substantially parallel to each other, spacing between the first and second semiconductor fins is smaller than spacing between the second and third semiconductor fins; depositing a first dielectric layer over top and sidewalls of the semiconductor fins, resulting in a trench between the second and third semiconductor fins, bottom and two opposing sidewalls of the trench being the first dielectric layer; implanting ions into one of the two opposing sidewalls of the trench by a first tilted ion implantation process; implanting ions into another one of the two opposing sidewalls of the trench by a second tilted ion implantation process; depositing a second dielectric layer into the trench, the first and second dielectric layers having different materials; and etching the first dielectric layer.