公开(公告)号：US20240322010A1

公开(公告)日：2024-09-26

申请号：US18731945

申请日：2024-06-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Chin Chang ,  Wei-Hao Wu ,  Li-Te Lin ,  Pinyen Lin

IPC: H01L29/66 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L29/66545 ,  H01L21/823431 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785

Abstract: A method includes removing a dummy gate to leave a trench between gate spacers, forming a gate dielectric extending into the trench, depositing a metal layer over the gate dielectric, with the metal layer including a portion extending into the trench, depositing a filling region into the trench, with the metal layer have a first and a second vertical portion on opposite sides of the filling region, etching back the metal layer, with the filling region at least recessed less than the metal layer, and remaining parts of the portion of the metal layer forming a gate electrode, depositing a dielectric material into the trench, and performing a planarization to remove excess portions of the dielectric material. A portion of the dielectric material in the trench forms at least a portion of a dielectric hard mask over the gate electrode.

公开(公告)号：US12033863B2

公开(公告)日：2024-07-09

申请号：US17572162

申请日：2022-01-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-Yu Lin ,  Yi-Ruei Jhan ,  Fang-Wei Lee ,  Li-Te Lin ,  Pinyen Lin ,  Tze-Chung Lin

IPC: H01L21/311 ,  C23C16/452 ,  H01L21/67 ,  H01L21/677

CPC classification number: H01L21/311 ,  C23C16/452 ,  H01L21/31116 ,  H01L21/67063 ,  H01L21/67069 ,  H01L21/67098 ,  H01L21/67103 ,  H01L21/67115 ,  H01L21/6719 ,  H01L21/67225 ,  H01L21/67248 ,  H01L21/67748

Abstract: The present disclosure provides a semiconductor fabrication apparatus. The semiconductor apparatus includes a processing chamber for etching; a substrate stage integrated in the processing chamber and being configured to secure a semiconductor wafer; a reflective mirror configured inside the processing chamber to reflect thermal energy from the heating mechanism toward the semiconductor wafer; and a heating mechanism embedded in the process chamber and is operable to perform a baking process to remove a by-product generated during the etching. The heating mechanism is integrated between the reflective mirror and a gas distribution plate of the processing chamber.

公开(公告)号：US11929424B2

公开(公告)日：2024-03-12

申请号：US17873962

申请日：2022-07-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yi-Chen Lo ,  Li-Te Lin ,  Pinyen Lin

IPC: H01L21/033 ,  H01L21/027 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/311 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/768 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66545 ,  H01L21/0274 ,  H01L21/0337 ,  H01L21/3065 ,  H01L21/3086 ,  H01L21/31122 ,  H01L21/3212 ,  H01L21/32136 ,  H01L21/76832 ,  H01L29/4236 ,  H01L29/66553 ,  H01L29/7851 ,  H01L29/7848

Abstract: A method includes forming a semiconductor fin on a substrate; forming a dielectric layer over the semiconductor fin; forming a metal gate electrode in the dielectric layer and extending across the semiconductor fin; forming a source/drain regions on the semiconductor fin and on opposite sides of the metal gate electrode; performing a first non-zero bias plasma etching process to the metal gate electrode; after performing the first non-zero bias plasma etching process, performing a first zero bias plasma etching process to the metal gate electrode.

公开(公告)号：US11925033B2

公开(公告)日：2024-03-05

申请号：US17217000

申请日：2021-03-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Liang Liu ,  Sheng-Chau Chen ,  Chung-Liang Cheng ,  Chia-Shiung Tsai ,  Yeong-Jyh Lin ,  Pinyen Lin ,  Huang-Lin Chao

IPC: H01L29/423 ,  H01L21/02 ,  H01L21/285 ,  H01L29/06 ,  H01L29/45 ,  H01L29/66 ,  H01L29/786 ,  H10B61/00

CPC classification number: H10B61/22 ,  H01L21/02603 ,  H01L21/28518 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66742 ,  H01L29/78696

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first and second transistors arranged over a substrate. The first transistor includes first channel structures extending between first and second source/drain regions. A first gate electrode is arranged between the first channel structures, and a first protection layer is arranged over a topmost one of the first channel structures. The second transistor includes second channel structures extending between the second source/drain region and a third source/drain region. A second gate electrode is arranged between the second channel structures, and a second protection layer is arranged over a topmost one of the second channel structures. The integrated chip further includes a first interconnect structure arranged between the substrate and the first and second channel structures, and a contact plug structure coupled to the second source/drain region and arranged above the first and second gate electrodes.

公开(公告)号：US20230068619A1

公开(公告)日：2023-03-02

申请号：US17459788

申请日：2021-08-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jung-Hao Chang ,  Fo-Ju Lin ,  Fang-Wei Lee ,  Li-Te Lin ,  Pinyen Lin

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/786 ,  H01L21/311

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The method can include forming a fin structure over a substrate. The fin structure can include first and second sacrificial layers. The method can further include forming a recess structure in a first portion of the fin structure, selectively etching the first sacrificial layer of a second portion of the fin structure over the second sacrificial layer of the second portion of the fin structure, and forming an inner spacer layer over the etched first sacrificial layer with the second sacrificial layer of the second portion of the fin structure being exposed.

公开(公告)号：US11551966B2

公开(公告)日：2023-01-10

申请号：US17000122

申请日：2020-08-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yi-Shan Chen ,  Chan-Syun David Yang ,  Li-Te Lin ,  Pinyen Lin

IPC: H01L23/48 ,  H01L21/768 ,  H01L21/311 ,  H01L21/033 ,  H01L23/528 ,  H01L21/32 ,  H01L21/02

Abstract: A semiconductor structure includes a semiconductor substrate, a metal layer, an interlayer dielectric (ILD) layer. The metal layer is disposed over the semiconductor substrate. The ILD layer is over the semiconductor substrate and laterally surrounding the metal layer, in which the ILD layer has a first portion in contact with a first sidewall of the metal layer and a second portion in contact with a second sidewall of the metal layer opposite to the first sidewall of the metal layer, and a width of the first portion of the ILD layer decreases as a distance from the semiconductor substrate increases.

公开(公告)号：US11522065B2

公开(公告)日：2022-12-06

申请号：US17207425

申请日：2021-03-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yi-Chen Lo ,  Jung-Hao Chang ,  Li-Te Lin ,  Pinyen Lin

IPC: H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/49 ,  H01L29/165 ,  H01L27/12 ,  H01L27/088 ,  H01L21/3065 ,  H01L21/02 ,  H01L21/28 ,  H01L21/67 ,  H01J37/00 ,  H01L21/8234 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/84

Abstract: A method includes following steps. First and second gate electrodes are formed over a substrate, with an ILD layer between the first and second gate electrodes. A first etch operation is performed to etch the first and second gate electrodes. A sacrificial layer is formed across the etched first and second gate electrodes and the ILD layer. A second etch operation is performed to etch the sacrificial layer and the etched the first and second gate electrodes.

公开(公告)号：US11417751B2

公开(公告)日：2022-08-16

申请号：US16837432

申请日：2020-04-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tze-Chung Lin ,  Han-Yu Lin ,  Li-Te Lin ,  Pinyen Lin

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/423

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a plurality of first semiconductor layers and a plurality of second semiconductor layers on a substrate, and the first semiconductor layers and the second semiconductor layers are alternately stacked. The method also includes forming a dummy gate structure over the first semiconductor layers and the second semiconductor layers. The method further includes removing a portion of the first semiconductor layers and second semiconductor layers to form a trench, and removing the second semiconductor layers to form a recess between two adjacent first semiconductor layers. The method includes forming a dummy dielectric layer in the recess, and removing a portion of the dummy dielectric layer to form a cavity. The method also includes forming an inner spacer layer in the cavity.

公开(公告)号：US11373902B2

公开(公告)日：2022-06-28

申请号：US16888929

申请日：2020-06-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hung-Chang Sun ,  Po-Chin Chang ,  Akira Mineji ,  Zi-Wei Fang ,  Pinyen Lin

IPC: H01L21/768 ,  H01L21/8234 ,  H01L23/532 ,  H01L23/535 ,  H01L27/088

Abstract: A semiconductor structure includes a semiconductor substrate, a gate structure, an etch stop layer, a dielectric structure, and a conductive material. The gate structure is on the semiconductor substrate. The etch stop layer is over the gate structure. The dielectric structure is over the etch stop layer, in which the dielectric structure has a ratio of silicon to nitrogen varying from a middle layer of the dielectric structure to a bottom layer of the dielectric structure. The conductive material extends through the dielectric structure.

公开(公告)号：US20210391447A1

公开(公告)日：2021-12-16

申请号：US17458087

申请日：2021-08-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-Yu Lin ,  Chansyun David Yang ,  Tze-Chung Lin ,  Fang-Wei Lee ,  Fo-Ju Lin ,  Li-Te Lin ,  Pinyen Lin

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/311 ,  H01L29/06

Abstract: A method of fabricating a semiconductor device includes forming a channel member suspended above a substrate, depositing a dielectric material layer wrapping around the channel member, performing an oxidation treatment to a surface portion of the dielectric material layer, selectively etching the surface portion of the dielectric material layer to expose sidewalls of the channel member, performing a nitridation treatment to remaining portions of the dielectric material layer and the exposed sidewalls of the channel member, thereby forming a nitride passivation layer partially wrapping around the channel member. The method also includes repeating the steps of performing the oxidation treatment and selectively etching until top and bottom surfaces of the channel member are exposed, removing the nitride passivation layer from the channel member, and forming a gate structure wrapping around the channel member.