公开(公告)号：US11961706B2

公开(公告)日：2024-04-16

申请号：US17245724

申请日：2021-04-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chansyun David Yang ,  Keh-Jeng Chang ,  Chan-Lon Yang ,  Perng-Fei Yuh

IPC: H01J37/08 ,  H01J37/305

CPC classification number: H01J37/3053 ,  H01J37/08 ,  H01J2237/1506 ,  H01J2237/20214 ,  H01J2237/3151

Abstract: The present disclosure relates to an ion beam etching (IBE) system including a plasma chamber configured to provide plasma, a screen grid, an extraction grid, an accelerator grid, and a decelerator grid. The screen grid receives a screen grid voltage to extract ions from the plasma within the plasma chamber to form an ion beam through a hole. The extraction grid receives an extraction grid voltage, where a voltage difference between the screen grid voltage and the extraction grid voltage determines an ion current density of the ion beam. The accelerator grid receives an accelerator grid voltage. A voltage difference between the extraction grid voltage and the accelerator grid voltage determines an ion beam energy for the ion beam. The IBE system can further includes a deflector system having a first deflector plate and a second deflector plate around a hole to control the direction of the ion beam.

公开(公告)号：US11916145B2

公开(公告)日：2024-02-27

申请号：US17815396

申请日：2022-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chansyun David Yang ,  Keh-Jeng Chang ,  Chan-Lon Yang

IPC: H01L29/78 ,  H01L21/8234 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L21/823431 ,  H01L29/66795 ,  H01L2029/7858

Abstract: The present disclosure describes a semiconductor device includes a first fin structure, an isolation structure in contact with a top surface of the first fin structure, a substrate layer in contact with the isolation structure, an epitaxial layer in contact with the isolation structure and the substrate layer, and a second fin structure above the first fin structure and in contact with the epitaxial layer.

公开(公告)号：US20220297234A1

公开(公告)日：2022-09-22

申请号：US17832832

申请日：2022-06-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chansyun David Yang ,  Li-Te Lin ,  Pinyen Lin

IPC: B23K26/348 ,  H01L21/3115 ,  B23K26/067 ,  B23K26/06 ,  H01L21/311

Abstract: A semiconductor fabrication apparatus includes a source chamber being operable to generate charged particles; and a processing chamber integrated with the source chamber and configured to receive the charged particles from the source chamber. The processing chamber includes a wafer stage being operable to secure and move a wafer, and a laser-charged particles interaction module that further includes a laser source to generate a first laser beam; a beam splitter configured to split the first laser beam into a second laser beam and a third laser beam; and a mirror configured to reflect the third laser beam such that the third laser beam is redirected to intersect with the second laser beam to form a laser interference pattern at a path of the charged particles, and wherein the laser interference pattern modulates the charged particles by in a micron-zone mode for processing the wafer using the modulated charged particles.

公开(公告)号：US11351635B2

公开(公告)日：2022-06-07

申请号：US16653401

申请日：2019-10-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chansyun David Yang ,  Li-Te Lin ,  Pinyen Lin

IPC: B23K26/348 ,  H01L21/3115 ,  B23K26/067 ,  B23K26/06 ,  H01L21/311

Abstract: A semiconductor fabrication apparatus includes a source chamber being operable to generate charged particles; and a processing chamber integrated with the source chamber and configured to receive the charged particles from the source chamber. The processing chamber includes a wafer stage being operable to secure and move a wafer, and a laser-charged particles interaction module that further includes a laser source to generate a first laser beam; a beam splitter configured to split the first laser beam into a second laser beam and a third laser beam; and a mirror configured to reflect the third laser beam such that the third laser beam is redirected to intersect with the second laser beam to form a laser interference pattern at a path of the charged particles, and wherein the laser interference pattern modulates the charged particles by in a micron-zone mode for processing the wafer using the modulated charged particles.

公开(公告)号：US20220013652A1

公开(公告)日：2022-01-13

申请号：US16925718

申请日：2020-07-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chansyun David Yang ,  Chan-Lon Yang ,  Keh-Jeng Chang

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/51 ,  H01L27/088 ,  H01L21/822 ,  H01L21/8234

Abstract: The present disclosure describes a method includes forming a fin structure including a fin base portion and a stacked fin portion on a substrate. The stacked fin portion includes a first semiconductor layer on the fin base portion, a second semiconductor layer above the first semiconductor layer, and a sacrificial semiconductor layer between the first and second semiconductor layers. The method further includes replacing the sacrificial semiconductor layer with a negative capacitance (NC) layer and forming gate electrodes around the NC layer, the first semiconductor layer, and the second semiconductor layer. The NC layer includes an NC dielectric material.

公开(公告)号：US11094796B2

公开(公告)日：2021-08-17

申请号：US16690441

申请日：2019-11-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chansyun David Yang

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L29/51

Abstract: The present disclosure describes a method for forming gate spacer structures with air-gaps to reduce the parasitic capacitance between the transistor's gate structures and the source/drain contacts. In some embodiments, the method includes forming a gate structure on a substrate and a spacer stack on sidewall surfaces of the gate structure—where the spacer stack comprises an inner spacer layer in contact with the gate structure, a sacrificial spacer layer on the inner spacer layer, and an outer spacer layer on the sacrificial spacer layer. The method further includes removing the sacrificial spacer layer to form an opening between the inner and outer spacer layers, depositing a polymer material on top surfaces of the inner and outer spacer layers, etching top sidewall surfaces of the inner and outer spacer layers to form a tapered top portion, and depositing a seal material.

公开(公告)号：US12027605B2

公开(公告)日：2024-07-02

申请号：US18362281

申请日：2023-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chansyun David Yang ,  Chan-Lon Yang ,  Keh-Jeng Chang

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L21/822

CPC classification number: H01L29/6653 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/513 ,  H01L29/66787 ,  H01L29/6681 ,  H01L29/7853 ,  H01L21/8221 ,  H01L29/516

Abstract: The present disclosure describes a method includes forming a fin structure including a fin base portion and a stacked fin portion on a substrate. The stacked fin portion includes a first semiconductor layer on the fin base portion, a second semiconductor layer above the first semiconductor layer, and a sacrificial semiconductor layer between the first and second semiconductor layers. The method further includes replacing the sacrificial semiconductor layer with a negative capacitance (NC) layer and forming gate electrodes around the NC layer, the first semiconductor layer, and the second semiconductor layer. The NC layer includes an NC dielectric material.

公开(公告)号：US11854910B2

公开(公告)日：2023-12-26

申请号：US17663608

申请日：2022-05-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chansyun David Yang ,  Keh-Jeng Chang ,  Chan-Lon Yang

IPC: H01L21/84 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L27/12 ,  H01L21/762

CPC classification number: H01L21/845 ,  H01L21/76256 ,  H01L21/76816 ,  H01L21/76898 ,  H01L23/5226 ,  H01L23/5286 ,  H01L27/1211

Abstract: The present disclosure describes a method to form a stacked semiconductor device with power rails. The method includes forming the stacked semiconductor device on a first surface of a substrate. The stacked semiconductor device includes a first fin structure, an isolation structure on the first fin structure, and a second fin structure above the first fin structure and in contact with the isolation structure. The first fin structure includes a first source/drain (S/D) region, and the second fin structure includes a second S/D region. The method also includes etching a second surface of the substrate and a portion of the first S/D region or the second S/D region to form an opening. The second surface is opposite to the first surface. The method further includes forming a dielectric barrier in the opening and forming an S/D contact in the opening.

公开(公告)号：US11791397B2

公开(公告)日：2023-10-17

申请号：US18175180

申请日：2023-02-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chansyun David Yang ,  Keh-Jeng Chang ,  Chan-Lon Yang

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/06 ,  H01L29/40 ,  H01L29/78 ,  H01L21/311 ,  H01L21/3065 ,  H01L21/02

CPC classification number: H01L29/66553 ,  H01L29/0653 ,  H01L29/408 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/6681 ,  H01L29/66545 ,  H01L29/7853 ,  H01L21/0228 ,  H01L21/02181 ,  H01L21/3065 ,  H01L21/31111 ,  H01L21/31116

Abstract: The structure of a semiconductor device with negative capacitance (NC) dielectric structures and a method of fabricating the semiconductor device are disclosed. A method of fabricating the semiconductor device includes forming a fin structure with a fin base portion and a fin top portion on a substrate, forming a spacer structure in a first region of the fin top portion, and forming a gate structure on a second region of the fin top portion. The spacer structure includes a first NC dielectric material and the gate structure includes a gate dielectric layer with a second NC dielectric material different from the first NC dielectric material.

公开(公告)号：US11769818B2

公开(公告)日：2023-09-26

申请号：US17815033

申请日：2022-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chansyun David Yang ,  Chan-Lon Yang ,  Keh-Jeng Chang

IPC: H01L29/06 ,  H01L29/51 ,  H01L29/66 ,  H01L29/423 ,  H01L29/78 ,  H01L21/822

CPC classification number: H01L29/6653 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/513 ,  H01L29/6681 ,  H01L29/66787 ,  H01L29/7853 ,  H01L21/8221 ,  H01L29/516

Abstract: The present disclosure describes a method includes forming a fin structure including a fin base portion and a stacked fin portion on a substrate. The stacked fin portion includes a first semiconductor layer on the fin base portion, a second semiconductor layer above the first semiconductor layer, and a sacrificial semiconductor layer between the first and second semiconductor layers. The method further includes replacing the sacrificial semiconductor layer with a negative capacitance (NC) layer and forming gate electrodes around the NC layer, the first semiconductor layer, and the second semiconductor layer. The NC layer includes an NC dielectric material.