公开(公告)号：US12183805B2

公开(公告)日：2024-12-31

申请号：US17333676

申请日：2021-05-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Zhi-Qiang Wu ,  Kuo-An Liu ,  Chan-Lon Yang ,  Bharath Kumar Pulicherla ,  Li-Te Lin ,  Chung-Cheng Wu ,  Gwan-Sin Chang ,  Pinyen Lin

IPC: H01L29/66 ,  H01L21/311 ,  H01L21/3213 ,  H01L29/40 ,  H01L29/49 ,  H01L29/78

Abstract: A semiconductor device includes a substrate having a semiconductor fin. A gate structure is over the semiconductor fin, in which the gate structure has a tapered profile and comprises a gate dielectric. A work function metal layer is over the gate dielectric, and a filling metal is over the work function metal layer. A gate spacer is along a sidewall of the gate structure, in which the work function metal layer is in contact with the gate dielectric and a top portion of the gate spacer. An epitaxy structure is over the semiconductor fin.

公开(公告)号：US20230378317A1

公开(公告)日：2023-11-23

申请号：US18362281

申请日：2023-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chansyun David Yang ,  Chan-Lon Yang ,  Keh-Jeng Chang

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/51 ,  H01L21/822

CPC classification number: H01L29/6653 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/6681 ,  H01L29/66787 ,  H01L29/7853 ,  H01L29/513 ,  H01L21/8221 ,  H01L29/516

Abstract: The present disclosure describes a method includes forming a fin structure including a fin base portion and a stacked fin portion on a substrate. The stacked fin portion includes a first semiconductor layer on the fin base portion, a second semiconductor layer above the first semiconductor layer, and a sacrificial semiconductor layer between the first and second semiconductor layers. The method further includes replacing the sacrificial semiconductor layer with a negative capacitance (NC) layer and forming gate electrodes around the NC layer, the first semiconductor layer, and the second semiconductor layer. The NC layer includes an NC dielectric material.

公开(公告)号：US20220367702A1

公开(公告)日：2022-11-17

申请号：US17815396

申请日：2022-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chansyun David Yang ,  Keh-Jeng Chang ,  Chan-Lon Yang

IPC: H01L29/78 ,  H01L21/8234 ,  H01L29/66

Abstract: The present disclosure describes a semiconductor device includes a first fin structure, an isolation structure in contact with a top surface of the first fin structure, a substrate layer in contact with the isolation structure, an epitaxial layer in contact with the isolation structure and the substrate layer, and a second fin structure above the first fin structure and in contact with the epitaxial layer.

公开(公告)号：US11502199B2

公开(公告)日：2022-11-15

申请号：US16885850

申请日：2020-05-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chansyun David Yang ,  Keh-Jeng Chang ,  Chan-Lon Yang

IPC: H01L29/78 ,  H01L21/8234 ,  H01L29/66

Abstract: The present disclosure describes a semiconductor device includes a first fin structure, an isolation structure in contact with a top surface of the first fin structure, a substrate layer in contact with the isolation structure, an epitaxial layer in contact with the isolation structure and the substrate layer, and a second fin structure above the first fin structure and in contact with the epitaxial layer.

公开(公告)号：US11437371B2

公开(公告)日：2022-09-06

申请号：US16925718

申请日：2020-07-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chansyun David Yang ,  Chan-Lon Yang ,  Keh-Jeng Chang

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/78 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L21/822

Abstract: The present disclosure describes a method includes forming a fin structure including a fin base portion and a stacked fin portion on a substrate. The stacked fin portion includes a first semiconductor layer on the fin base portion, a second semiconductor layer above the first semiconductor layer, and a sacrificial semiconductor layer between the first and second semiconductor layers. The method further includes replacing the sacrificial semiconductor layer with a negative capacitance (NC) layer and forming gate electrodes around the NC layer, the first semiconductor layer, and the second semiconductor layer. The NC layer includes an NC dielectric material.

公开(公告)号：US11282711B2

公开(公告)日：2022-03-22

申请号：US16944653

申请日：2020-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chansyun David Yang ,  Keh-Jeng Chang ,  Chan-Lon Yang

IPC: H01L21/311 ,  H01L21/67 ,  H01L21/683 ,  H01L21/02 ,  H01J37/32

Abstract: The present disclosure describes methods and systems for plasma-assisted etching of a metal oxide. The method includes modifying a surface of the metal oxide with a first gas, removing a top portion of the metal oxide by a ligand exchange reaction, and cleaning the surface of the metal oxide with a second gas.

公开(公告)号：US20220059414A1

公开(公告)日：2022-02-24

申请号：US16997062

申请日：2020-08-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chansyun David YANG ,  Keh-Jeng Chang ,  Chan-Lon Yang

IPC: H01L21/84 ,  H01L21/768 ,  H01L21/762 ,  H01L23/528 ,  H01L27/12 ,  H01L23/522

Abstract: The present disclosure describes a method to form a stacked semiconductor device with power rails. The method includes forming the stacked semiconductor device on a first surface of a substrate. The stacked semiconductor device includes a first fin structure, an isolation structure on the first fin structure, and a second fin structure above the first fin structure and in contact with the isolation structure. The first fin structure includes a first source/drain (S/D) region, and the second fin structure includes a second S/D region. The method also includes etching a second surface of the substrate and a portion of the first S/D region or the second S/D region to form an opening. The second surface is opposite to the first surface. The method further includes forming a dielectric barrier in the opening and forming an S/D contact in the opening.

公开(公告)号：US11961706B2

公开(公告)日：2024-04-16

申请号：US17245724

申请日：2021-04-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chansyun David Yang ,  Keh-Jeng Chang ,  Chan-Lon Yang ,  Perng-Fei Yuh

IPC: H01J37/08 ,  H01J37/305

CPC classification number: H01J37/3053 ,  H01J37/08 ,  H01J2237/1506 ,  H01J2237/20214 ,  H01J2237/3151

Abstract: The present disclosure relates to an ion beam etching (IBE) system including a plasma chamber configured to provide plasma, a screen grid, an extraction grid, an accelerator grid, and a decelerator grid. The screen grid receives a screen grid voltage to extract ions from the plasma within the plasma chamber to form an ion beam through a hole. The extraction grid receives an extraction grid voltage, where a voltage difference between the screen grid voltage and the extraction grid voltage determines an ion current density of the ion beam. The accelerator grid receives an accelerator grid voltage. A voltage difference between the extraction grid voltage and the accelerator grid voltage determines an ion beam energy for the ion beam. The IBE system can further includes a deflector system having a first deflector plate and a second deflector plate around a hole to control the direction of the ion beam.

公开(公告)号：US11916145B2

公开(公告)日：2024-02-27

申请号：US17815396

申请日：2022-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chansyun David Yang ,  Keh-Jeng Chang ,  Chan-Lon Yang

IPC: H01L29/78 ,  H01L21/8234 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L21/823431 ,  H01L29/66795 ,  H01L2029/7858

Abstract: The present disclosure describes a semiconductor device includes a first fin structure, an isolation structure in contact with a top surface of the first fin structure, a substrate layer in contact with the isolation structure, an epitaxial layer in contact with the isolation structure and the substrate layer, and a second fin structure above the first fin structure and in contact with the epitaxial layer.

公开(公告)号：US11489074B2

公开(公告)日：2022-11-01

申请号：US16995774

申请日：2020-08-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kun-Mu Li ,  Tsz-Mei Kwok ,  Ming-Hua Yu ,  Chan-Lon Yang

IPC: H01L29/78 ,  H01L21/84 ,  H01L29/06 ,  H01L21/02 ,  H01L21/3115 ,  H01L27/12 ,  H01L29/66 ,  H01L29/165

Abstract: A fin field effect transistor (Fin FET) device includes a fin structure extending in a first direction and protruding from an isolation insulating layer disposed over a substrate. The fin structure includes a well layer, an oxide layer disposed over the well layer and a channel layer disposed over the oxide layer. The Fin FET device includes a gate structure covering a portion of the fin structure and extending in a second direction perpendicular to the first direction. The Fin FET device includes a source and a drain. Each of the source and drain includes a stressor layer disposed in recessed portions formed in the fin structure. The stressor layer extends above the recessed portions and applies a stress to a channel layer of the fin structure under the gate structure. The Fin FET device includes a dielectric layer formed in contact with the oxide layer and the stressor layer in the recessed portions.