公开(公告)号：US20220320180A1

公开(公告)日：2022-10-06

申请号：US17217000

申请日：2021-03-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Liang Liu ,  Sheng-Chau Chen ,  Chung-Liang Cheng ,  Chia-Shiung Tsai ,  Yeong-Jyh Lin ,  Pinyen Lin ,  Huang-Lin Chao

IPC: H01L27/22 ,  H01L29/06 ,  H01L29/423 ,  H01L29/45 ,  H01L29/786 ,  H01L21/02 ,  H01L21/285 ,  H01L29/66

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first and second transistors arranged over a substrate. The first transistor includes first channel structures extending between first and second source/drain regions. A first gate electrode is arranged between the first channel structures, and a first protection layer is arranged over a topmost one of the first channel structures. The second transistor includes second channel structures extending between the second source/drain region and a third source/drain region. A second gate electrode is arranged between the second channel structures, and a second protection layer is arranged over a topmost one of the second channel structures. The integrated chip further includes a first interconnect structure arranged between the substrate and the first and second channel structures, and a contact plug structure coupled to the second source/drain region and arranged above the first and second gate electrodes.

公开(公告)号：US11742321B2

公开(公告)日：2023-08-29

申请号：US17319558

申请日：2021-05-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Xin-Hua Huang ,  Kuan-Liang Liu ,  Kuo Liang Lu ,  Ping-Yin Liu

IPC: B23K37/00 ,  H01L23/00 ,  B23K37/04 ,  H01L21/683 ,  H01L21/67 ,  H01L21/20 ,  H01L21/762 ,  B23K101/40

CPC classification number: H01L24/94 ,  B23K37/04 ,  B23K37/0408 ,  H01L21/2007 ,  H01L21/67092 ,  H01L21/6831 ,  H01L21/6838 ,  H01L21/76251 ,  H01L24/75 ,  H01L24/83 ,  B23K2101/40 ,  H01L2224/753 ,  H01L2224/759 ,  H01L2224/75704 ,  H01L2224/75724 ,  H01L2224/75744 ,  H01L2224/83209 ,  H01L2224/83894 ,  H01L2224/83908 ,  H01L2924/1203 ,  H01L2924/12043 ,  H01L2924/1304 ,  H01L2924/1434 ,  H01L2924/1461 ,  H01L2924/00012 ,  H01L2924/12043 ,  H01L2924/00012 ,  H01L2924/1434 ,  H01L2924/00012 ,  H01L2924/1461 ,  H01L2924/00012

Abstract: The present disclosure, in some embodiments, relates to a workpiece bonding apparatus. The workpieces bonding apparatus includes a first substrate holder having a first surface configured to receive a first workpiece, and a second substrate holder having a second surface configured to receive a second workpiece. A vacuum apparatus is positioned between the first substrate holder and the second substrate holder and is configured to selectively induce a vacuum between the first surface and the second surface. The vacuum is configured to attract the first surface and the second surface toward one another.

公开(公告)号：US11495489B2

公开(公告)日：2022-11-08

申请号：US16732696

申请日：2020-01-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ta Wu ,  Chia-Shiung Tsai ,  Jiech-Fun Lu ,  Kuan-Liang Liu ,  Shih-Pei Chou ,  Yu-Hung Cheng ,  Yeur-Luen Tu

IPC: H01L21/00 ,  H01L21/762 ,  H01L21/3213 ,  H01L21/306

Abstract: Various embodiments of the present application are directed towards a method for forming a semiconductor-on-insulator (SOI) substrate with a thick device layer and a thick insulator layer. In some embodiments, the method includes forming an insulator layer covering a handle substrate, and epitaxially forming a device layer on a sacrificial substrate. The sacrificial substrate is bonded to a handle substrate, such that the device layer and the insulator layer are between the sacrificial and handle substrates, and the sacrificial substrate is removed. The removal includes performing an etch into the sacrificial substrate until the device layer is reached. Because the device layer is formed by epitaxy and transferred to the handle substrate, the device layer may be formed with a large thickness. Further, because the epitaxy is not affected by the thickness of the insulator layer, the insulator layer may be formed with a large thickness.

公开(公告)号：US10553474B1

公开(公告)日：2020-02-04

申请号：US16139357

申请日：2018-09-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ta Wu ,  Chia-Shiung Tsai ,  Jiech-Fun Lu ,  Kuan-Liang Liu ,  Shih-Pei Chou ,  Yu-Hung Cheng ,  Yeur-Luen Tu

IPC: H01L21/762 ,  H01L21/3213

Abstract: Various embodiments of the present application are directed towards a method for forming a semiconductor-on-insulator (SOI) substrate with a thick device layer and a thick insulator layer. In some embodiments, the method includes forming an insulator layer covering a handle substrate, and epitaxially forming a device layer on a sacrificial substrate. The sacrificial substrate is bonded to a handle substrate, such that the device layer and the insulator layer are between the sacrificial and handle substrates, and the sacrificial substrate is removed. The removal includes performing an etch into the sacrificial substrate until the device layer is reached. Because the device layer is formed by epitaxy and transferred to the handle substrate, the device layer may be formed with a large thickness. Further, because the epitaxy is not affected by the thickness of the insulator layer, the insulator layer may be formed with a large thickness.

公开(公告)号：US20210193684A1

公开(公告)日：2021-06-24

申请号：US17192333

申请日：2021-03-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Liang Liu ,  Yeur-Luen Tu

IPC: H01L27/12 ,  H01L21/762

Abstract: Various embodiments of the present disclosure are directed towards a semiconductor wafer. The semiconductor wafer comprises a handle wafer. A first oxide layer is disposed over the handle wafer. A device layer is disposed over the first oxide layer. A second oxide layer is disposed between the first oxide layer and the device layer, wherein the first oxide layer has a first etch rate for an etch process and the second oxide layer has a second etch rate for the etch process, and wherein the second etch rate is greater than the first etch rate.

公开(公告)号：US11031369B2

公开(公告)日：2021-06-08

申请号：US16654377

申请日：2019-10-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Xin-Hua Huang ,  Kuan-Liang Liu ,  Kuo Liang Lu ,  Ping-Yin Liu

IPC: B23K37/04 ,  H01L23/00 ,  H01L21/683 ,  H01L21/67 ,  H01L21/20 ,  H01L21/762 ,  B23K101/40

Abstract: An apparatus and method is provided for controlling a propagation of a bond wave during semiconductor processing. The apparatus has a first chuck to selectively retain a first workpiece. A second chuck selectively retains a second workpiece. The first and second chucks selectively secure at least a periphery of the respective first workpiece and second workpiece. An air vacuum is circumferentially located in a region between the first chuck and second chuck. The air vacuum is configured to induce a vacuum between the first workpiece and second workpiece to selectively bring the first workpiece and second workpiece together from a propagation point. The air vacuum can be localized air vacuum guns, a vacuum disk, or an air curtain positioned about the periphery of the region between the first chuck and second chuck. The air curtain induces a lower pressure within the region between the first and second chucks.

公开(公告)号：US20210091118A1

公开(公告)日：2021-03-25

申请号：US16580259

申请日：2019-09-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Liang Liu ,  Yeur-Luen Tu

IPC: H01L27/12 ,  H01L21/762

Abstract: Various embodiments of the present disclosure are directed towards a semiconductor wafer. The semiconductor wafer comprises a handle wafer. A first oxide layer is disposed over the handle wafer. A device layer is disposed over the first oxide layer. A second oxide layer is disposed between the first oxide layer and the device layer, wherein the first oxide layer has a first etch rate for an etch process and the second oxide layer has a second etch rate for the etch process, and wherein the second etch rate is greater than the first etch rate.

公开(公告)号：US10950631B1

公开(公告)日：2021-03-16

申请号：US16580259

申请日：2019-09-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Liang Liu ,  Yeur-Luen Tu

IPC: H01L27/12 ,  H01L21/762

Abstract: Various embodiments of the present disclosure are directed towards a semiconductor wafer. The semiconductor wafer comprises a handle wafer. A first oxide layer is disposed over the handle wafer. A device layer is disposed over the first oxide layer. A second oxide layer is disposed between the first oxide layer and the device layer, wherein the first oxide layer has a first etch rate for an etch process and the second oxide layer has a second etch rate for the etch process, and wherein the second etch rate is greater than the first etch rate.

公开(公告)号：US20200350302A1

公开(公告)日：2020-11-05

申请号：US16933082

申请日：2020-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Ming Wu ,  Kuan-Liang Liu ,  Wen-De Wang ,  Yung-Lung Lin

IPC: H01L25/00 ,  H01L23/58 ,  H01L23/00

Abstract: Some embodiments relate to a three-dimensional (3D) integrated circuit (IC). The 3D IC includes a first IC die comprising a first semiconductor substrate, and a first interconnect structure over the first semiconductor substrate. The 3D IC also includes a second IC die comprising a second semiconductor substrate, and a second interconnect structure that separates the second semiconductor substrate from the first interconnect structure. A seal ring structure separates the first interconnect structure from the second interconnect structure and perimetrically surrounds a gas reservoir between the first IC die and second IC die. The seal ring structure includes a sidewall gas-vent opening structure configured to allow gas to pass between the gas reservoir and an ambient environment surrounding the 3D IC.

公开(公告)号：US10790240B2

公开(公告)日：2020-09-29

申请号：US15462078

申请日：2017-03-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Ming Wu ,  Kuan-Liang Liu ,  Pao-Tung Chen

IPC: H01L23/12 ,  H01L23/52 ,  H01L29/40 ,  H01L23/00 ,  H01L23/58 ,  H01L25/065

Abstract: A hybrid-bonding structure and a method for forming a hybrid-bonding structure are provided. The hybrid-bonding structure includes a first semiconductor substrate, a first conductive line and a first dielectric dummy pattern. The first conductive line is formed over the first semiconductor substrate. A surface of the first conductive line is configured to hybrid-bond with a second conductive line over a second semiconductor substrate. The first dielectric dummy pattern is formed over the first semiconductor substrate and embedded in the first conductive line.