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公开(公告)号：US20220231067A1
公开(公告)日：2022-07-21
申请号：US17233787
申请日：2021-04-19
发明人： Sin-Yao Huang , Hung-Ling Shih , Kuo-Ming Wu , Hung-Wen Hsu
IPC分类号： H01L27/146
摘要： Various embodiments of the present disclosure are directed towards an integrated circuit (IC) chip comprising a stilted pad structure. A wire underlies a semiconductor substrate on a frontside of the semiconductor substrate. Further, a trench isolation structure extends into the frontside of the semiconductor substrate. The stilted pad structure is inset into a backside of the semiconductor substrate that is opposite the frontside. The stilted pad structure comprises a pad body and a pad protrusion. The pad protrusion underlies the pad body and protrudes from the pad body, through a portion of the semiconductor substrate and the trench isolation structure, towards the wire. The pad body overlies the portion of the semiconductor substrate and is separated from the trench isolation structure by the portion of the semiconductor substrate.
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公开(公告)号：US11152276B2
公开(公告)日：2021-10-19
申请号：US16785866
申请日：2020-02-10
IPC分类号： H01L23/31 , H01L23/48 , H01L21/768 , H01L23/528 , H01L21/56 , H01L25/065
摘要： The present disclosure, in some embodiments, relates to a method of forming an integrated chip structure. The method may be performed by forming a plurality of interconnect layers within a first interconnect structure disposed over an upper surface of a first semiconductor substrate. An edge trimming process is performed to remove parts of the first interconnect structure and the first semiconductor substrate along a perimeter of the first semiconductor substrate. The edge trimming process results in the first semiconductor substrate having a recessed surface coupled to the upper surface by way of an interior sidewall disposed directly over the first semiconductor substrate. A dielectric protection layer is formed onto a sidewall of the first interconnect structure after performing the edge trimming process.
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公开(公告)号：US11139210B2
公开(公告)日：2021-10-05
申请号：US16908966
申请日：2020-06-23
IPC分类号： H01L21/822 , H01L23/532 , H01L23/528 , H01L23/522 , H01L21/768 , H01L23/00 , H01L25/065
摘要： In some embodiments, a method for bonding semiconductor wafers is provided. The method includes forming a first integrated circuit (IC) over a central region of a first semiconductor wafer. A first ring-shaped bonding support structure is formed over a ring-shaped peripheral region of the first semiconductor wafer, where the ring-shaped peripheral region of the first semiconductor wafer encircles the central region of the first semiconductor wafer. A second semiconductor wafer is bonded to the first semiconductor wafer, such that a second IC arranged on the second semiconductor wafer is electrically coupled to the first IC.
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公开(公告)号：US20210134694A1
公开(公告)日：2021-05-06
申请号：US16785866
申请日：2020-02-10
IPC分类号： H01L23/31 , H01L23/48 , H01L25/065 , H01L23/528 , H01L21/56 , H01L21/768
摘要： The present disclosure, in some embodiments, relates to a method of forming an integrated chip structure. The method may be performed by forming a plurality of interconnect layers within a first interconnect structure disposed over an upper surface of a first semiconductor substrate. An edge trimming process is performed to remove parts of the first interconnect structure and the first semiconductor substrate along a perimeter of the first semiconductor substrate. The edge trimming process results in the first semiconductor substrate having a recessed surface coupled to the upper surface by way of an interior sidewall disposed directly over the first semiconductor substrate. A dielectric protection layer is formed onto a sidewall of the first interconnect structure after performing the edge trimming process.
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公开(公告)号：US20200312817A1
公开(公告)日：2020-10-01
申请号：US16902539
申请日：2020-06-16
发明人： Kuo-Ming Wu , Ching-Chun Wang , Dun-Nian Yaung , Hsing-Chih Lin , Jen-Cheng Liu , Min-Feng Kao , Yung-Lung Lin , Shih-Han Huang , I-Nan Chen
IPC分类号： H01L25/065 , H01L23/528 , H01L23/48 , H01L25/00 , H01L23/00 , H01L23/532
摘要： A three-dimensional (3D) integrated circuit (IC) is provided. In some embodiments, a second IC die is bonded to a first IC die by a first bonding structure. A third IC die is bonded to the second IC die by a second bonding structure. The second bonding structure is arranged between back sides of the second IC die and the third IC die opposite to corresponding interconnect structures and comprises a first TSV (through substrate via) disposed through a second substrate of the second IC die and a second TSV disposed through a third substrate of the third IC die. The second bonding structure further comprises conductive features with oppositely titled sidewalls disposed between the first TSV and the second TSV.
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公开(公告)号：US10727205B2
公开(公告)日：2020-07-28
申请号：US15998455
申请日：2018-08-15
发明人： Kuo-Ming Wu , Ching-Chun Wang , Dun-Nian Yaung , Hsing-Chih Lin , Jen-Cheng Liu , Min-Feng Kao , Yung-Lung Lin , Shih-Han Huang , I-Nan Chen
IPC分类号： H01L25/065 , H01L23/528 , H01L23/48 , H01L23/532 , H01L25/00 , H01L23/00
摘要： A three-dimensional (3D) integrated circuit (IC) is provided. In some embodiments, a second IC die is bonded to a first IC die by a first bonding structure. The first bonding structure contacts a first interconnect structure of the first IC die and a second interconnection structure of the second IC die, and has a first portion and a second portion hybrid bonded together. A third IC die is bonded to the second IC die by a third bonding structure. The third bonding structure comprises a second TSV (through substrate via) disposed through the second substrate of the second IC die and includes varies bonding structures according to varies embodiments of the invention.
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公开(公告)号：US10535730B2
公开(公告)日：2020-01-14
申请号：US15964636
申请日：2018-04-27
发明人： Karthick Murukesan , Wen-Chih Chiang , Chun Lin Tsai , Ker-Hsiao Huo , Kuo-Ming Wu , Po-Chih Chen , Ru-Yi Su , Shiuan-Jeng Lin , Yi-Min Chen , Hung-Chou Lin , Yi-Cheng Chiu
摘要： Various embodiments of the present application are directed towards an integrated circuit (IC) in which a high voltage metal-oxide-semiconductor (HVMOS) device is integrated with a high voltage junction termination (HVJT) device. In some embodiments, a first drift well and a second drift well are in a substrate. The first and second drift wells border in a ring-shaped pattern and have a first doping type. A peripheral well is in the substrate and has a second doping type opposite the first doping type. The peripheral well surrounds and separates the first and second drift wells. A body well is in the substrate and has the second doping type. Further, the body well overlies the first drift well and is spaced from the peripheral well by the first drift well. A gate electrode overlies a junction between the first drift well and the body well.
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公开(公告)号：US20190109189A1
公开(公告)日：2019-04-11
申请号：US16199483
申请日：2018-11-26
发明人： Yi-Cheng Chiu , Wen-Chih Chiang , Chun Lin Tsai , Kuo-Ming Wu , Shiuan-Jeng Lin , Yi-Min Chen , Hung-Chou Lin , Karthick Murukesan
IPC分类号： H01L29/06 , H01L29/66 , H01L29/78 , H01L23/522 , H01L29/10 , H01L23/528
摘要： The present disclosure, in some embodiments, relates to a high voltage resistor device. The device includes a buried well region disposed within a substrate and having a first doping type. A drift region is disposed within the substrate and contacts the buried well region. The drift region has the first doping type. A body region is disposed within the substrate and has a second doping type. The body region laterally contacts the drift region and vertically contacts the buried well region. An isolation structure is over the drift region and a resistor structure is over the isolation structure.
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公开(公告)号：US11610812B2
公开(公告)日：2023-03-21
申请号：US17038198
申请日：2020-09-30
IPC分类号： H01L21/00 , H01L21/768 , H01L25/00 , H01L23/528 , H01L23/48 , H01L23/522 , H01L23/00 , H01L25/065
摘要： The present disclosure, in some embodiments, relates to a method of forming an integrated chip structure. The method may be performed by forming a plurality of interconnect layers within a first interconnect structure disposed over an upper surface of a first semiconductor substrate. An edge trimming process is performed to remove parts of the first interconnect structure and the first semiconductor substrate along a perimeter of the first semiconductor substrate. The edge trimming process results in the first semiconductor substrate having a recessed surface coupled to the upper surface by way of an interior sidewall disposed directly over the first semiconductor substrate. A dielectric capping structure is formed onto a sidewall of the first interconnect structure after performing the edge trimming process.
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公开(公告)号：US20220362887A1
公开(公告)日：2022-11-17
申请号：US17317977
申请日：2021-05-12
发明人： Kuo-Ming Wu , Yung-Lung Lin , Hau-Yi Hsiao , Sheng-Chau Chen , Cheng-Yuan Tsai
IPC分类号： B23K26/361 , H01L21/02 , B23K26/062 , B23K26/035 , H01L21/66
摘要： In some embodiments, the present disclosure relates to a wafer edge trimming apparatus that includes a processing chamber defined by chamber housing. Within the processing chamber is a wafer chuck configured to hold onto a wafer structure. Further, a blade is arranged near an edge of the wafer chuck and configured to remove an edge potion of the wafer structure and to define a new sidewall of the wafer structure. A laser sensor apparatus is configured to direct a laser beam directed toward a top surface of the wafer chuck. The laser sensor apparatus is configured to measure a parameter of an analysis area of the wafer structure. Control circuitry is to the laser sensor apparatus and the blade. The control circuitry is configured to start a damage prevention process when the parameter deviates from a predetermined threshold value by at least a predetermined shift value.
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