-
公开(公告)号：US20230154898A1
公开(公告)日：2023-05-18
申请号：US18156848
申请日：2023-01-19
发明人： Kuo-Ming Wu , Yung-Lung Lin , Zhi-Yang Wang , Sheng-Chau Chen , Cheng-Hsien Chou
IPC分类号： H01L25/065 , H01L25/00 , H01L23/00
CPC分类号： H01L25/0657 , H01L25/50 , H01L24/06 , H01L24/02
摘要： A structure and a method of forming are provided. The structure includes a first dielectric layer overlying a first substrate. A first connection pad is disposed in a top surface of the first dielectric layer and contacts a first redistribution line. A first dummy pad is disposed in the top surface of the first dielectric layer, the first dummy pad contacting the first redistribution line. A second dielectric layer overlies a second substrate. A second connection pad and a second dummy pad are disposed in the top surface of the second dielectric layer, the second connection pad bonded to the first connection pad, and the first dummy pad positioned in a manner that is offset from the second dummy pad so that the first dummy pad and the second dummy pad do not contact each other.
-
公开(公告)号：US11189583B2
公开(公告)日：2021-11-30
申请号：US16723041
申请日：2019-12-20
发明人： Sheng-Chau Chen , Shih-Pei Chou , Ming-Che Lee , Kuo-Ming Wu , Cheng-Hsien Chou , Cheng-Yuan Tsai , Yeur-Luen Tu
IPC分类号： H01L23/48 , H01L23/00 , H01L25/065 , H01L25/00 , H01L21/768
摘要： The present disclosure provides a semiconductor structure. The semiconductor structure comprises a semiconductive substrate and an interconnect structure over the semiconductive substrate. The semiconductor structure also comprises a bond pad in the semiconductive substrate and coupled to the metal layer. The bond pad comprises two conductive layers.
-
公开(公告)号：US11127635B1
公开(公告)日：2021-09-21
申请号：US16866685
申请日：2020-05-05
发明人： Yung-Lung Lin , Cheng-Hsien Chou , Cheng-Yuan Tsai , Kuo-Ming Wu , Hau-Yi Hsiao
IPC分类号： H01L21/822 , H01L21/304 , H01L29/06 , H01L27/06
摘要： The present disclosure relates to a method for forming a multi-dimensional integrated chip structure. In some embodiments, the method may be performed by bonding a second substrate to an upper surface of a first substrate. A first edge trimming cut is performed along a first loop and extends into a first peripheral portion of the second substrate. A second edge trimming cut is performed along a second loop and extends into a second peripheral portion of the second substrate and into the first substrate. A third edge trimming cut is performed along a third loop and extends into a third peripheral portion of the first substrate.
-
公开(公告)号：US20210272996A1
公开(公告)日：2021-09-02
申请号：US16848903
申请日：2020-04-15
发明人： Tsun-Kai Tsao , Cheng-Hsien Chou , Jiech-Fun Lu
IPC分类号： H01L27/146
摘要： Various embodiments of the present disclosure are directed towards an image sensor having a photodetector disposed within a substrate. The substrate has a front-side surface and a back-side surface. An absorption enhancement structure is disposed along the back-side surface of the substrate and overlies the photodetector. The absorption enhancement structure includes a plurality of protrusions that extend outwardly from the back-side surface of the substrate. Each protrusion comprises opposing curved sidewalls.
-
公开(公告)号：US20210225919A1
公开(公告)日：2021-07-22
申请号：US17219960
申请日：2021-04-01
发明人： Sheng-Chan Li , Cheng-Hsien Chou , Cheng-Yuan Tsai , Keng-Yu Chou , Yeur-Luen Tu
IPC分类号： H01L27/146
摘要： The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a photodetector arranged within a substrate. The substrate has surfaces defining one or more protrusions arranged along a first side of the substrate over the photodetector. One or more isolation structures are arranged within one or more trenches defined by sidewalls of the substrate arranged on opposing sides of the photodetector. The one or more trenches extend from the first side of the substrate to within the substrate. The one or more isolation structures respectively include a reflective medium configured to reflect electromagnetic radiation.
-
公开(公告)号：US10964746B2
公开(公告)日：2021-03-30
申请号：US16405102
申请日：2019-05-07
发明人： Cheng-Hsien Chou , Shih Pei Chou , Chih-Yu Lai , Sheng-Chau Chen , Chih-Ta Chen , Yeur-Luen Tu , Chia-Shiung Tsai
IPC分类号： H01L27/146 , H01L33/20 , H01L21/8238
摘要： Some embodiments of the present disclosure relate to a method in which a functional layer is formed over an upper semiconductor surface of a semiconductor substrate, and a capping layer is formed over the functional layer. A first etchant is used to form a recess through the capping layer and through the functional layer. The recess has a first depth and exposes a portion of the semiconductor substrate there through. A protective layer is formed along a lower surface and inner sidewalls of the recess. A second etchant is used to remove the protective layer from the lower surface of the recess and to extend the recess below the upper semiconductor surface to a second depth to form a deep trench. To prevent etching of the functional layer, the protective layer remains in place along the inner sidewalls of the recess while the second etchant is used.
-
公开(公告)号：US20200006145A1
公开(公告)日：2020-01-02
申请号：US16178819
申请日：2018-11-02
IPC分类号： H01L21/822 , H01L23/532 , H01L23/528 , H01L23/522 , H01L21/768 , H01L25/065 , H01L23/00
摘要： In some embodiments, a method for bonding semiconductor wafers is provided. The method includes forming a first integrated circuit (IC) over a central region of a first semiconductor wafer. A first ring-shaped bonding support structure is formed over a ring-shaped peripheral region of the first semiconductor wafer, where the ring-shaped peripheral region of the first semiconductor wafer encircles the central region of the first semiconductor wafer. A second semiconductor wafer is bonded to the first semiconductor wafer, such that a second IC arranged on the second semiconductor wafer is electrically coupled to the first IC.
-
公开(公告)号：US20190067355A1
公开(公告)日：2019-02-28
申请号：US15688077
申请日：2017-08-28
发明人： Sheng-Chan Li , Cheng-Hsien Chou , Cheng-Yuan Tsai , Keng-Yu Chou , Yeur-Luen Tu
IPC分类号： H01L27/146
摘要： The present disclosure relates to an image sensor integrated chip having a deep trench isolation (DTI) structure having a reflective element. In some embodiments, the image sensor integrated chip includes an image sensing element arranged within a substrate. A plurality of protrusions are arranged along a first side of the substrate over the image sensing element and one or more absorption enhancement layers are arranged over and between the plurality of protrusions. A plurality of DTI structures are arranged within trenches disposed on opposing sides of the image sensing element and extend from the first side of the substrate to within the substrate. The plurality of DTI structures respectively include a reflective element having one or more reflective regions configured to reflect electromagnetic radiation. By reflecting electromagnetic radiation using the reflective elements, cross-talk between adjacent pixel regions is reduced, thereby improving performance of the image sensor integrated chip.
-
公开(公告)号：US10204822B2
公开(公告)日：2019-02-12
申请号：US15884304
申请日：2018-01-30
发明人： Cheng-Hsien Chou , Hung-Ling Shih , Tsun-Kai Tsao , Ming-Huei Shen , Kuo-Hwa Tzeng , Yeur-Luen Tu
IPC分类号： H01L21/02 , H01L21/762
摘要： In a method for fabricating a semiconductor device, a trench is etched in a semiconductor substrate having a top surface, and a lining oxide layer is formed conformal to the trench. A negatively-charged liner covering the lining oxide layer and conformal to the trench is formed. The trench is partially filled with a flowable oxide to a level below the top surface of the semiconductor substrate, and the flowable oxide in the trench is cured. The negatively-charged liner above the cured flowable oxide is optionally removed. A silicon oxide is deposited in the remaining portion of the trench, and a planarization process is performed to remove excess portions of the silicon oxide over the top surface of the semiconductor substrate.
-
公开(公告)号：US20180061877A1
公开(公告)日：2018-03-01
申请号：US15803995
申请日：2017-11-06
发明人： Cheng-Hsien Chou , Wen-I Hsu , Tsun-Kai Tsao , Chih-Yu Lai , Jiech-Fun Lu , Yeur-Luen Tu
IPC分类号： H01L27/146 , H01L31/18
CPC分类号： H01L27/14614 , H01L27/14636 , H01L27/14643 , H01L27/14689 , H01L31/18
摘要： In some embodiments, the present disclosure relates to a method of forming an integrated chip. The method is performed by forming a gate dielectric layer over a substrate, and selectively forming a gate material over the gate dielectric layer. A gate dielectric protection layer is formed over the gate dielectric layer, and a first sidewall spacer is formed over the gate dielectric protection layer and flanking a side of the gate material. The gate dielectric protection layer continuously extends from between the first sidewall spacer and the gate dielectric layer to outside of the first sidewall spacer.
-
-
-
-
-
-
-
-
-
搜索结果
57 条记录 (耗时 0.033 秒)
