公开(公告)号：US10964746B2

公开(公告)日：2021-03-30

申请号：US16405102

申请日：2019-05-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Hsien Chou ,  Shih Pei Chou ,  Chih-Yu Lai ,  Sheng-Chau Chen ,  Chih-Ta Chen ,  Yeur-Luen Tu ,  Chia-Shiung Tsai

IPC: H01L27/146 ,  H01L33/20 ,  H01L21/8238

Abstract: Some embodiments of the present disclosure relate to a method in which a functional layer is formed over an upper semiconductor surface of a semiconductor substrate, and a capping layer is formed over the functional layer. A first etchant is used to form a recess through the capping layer and through the functional layer. The recess has a first depth and exposes a portion of the semiconductor substrate there through. A protective layer is formed along a lower surface and inner sidewalls of the recess. A second etchant is used to remove the protective layer from the lower surface of the recess and to extend the recess below the upper semiconductor surface to a second depth to form a deep trench. To prevent etching of the functional layer, the protective layer remains in place along the inner sidewalls of the recess while the second etchant is used.

公开(公告)号：US20180061877A1

公开(公告)日：2018-03-01

申请号：US15803995

申请日：2017-11-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Hsien Chou ,  Wen-I Hsu ,  Tsun-Kai Tsao ,  Chih-Yu Lai ,  Jiech-Fun Lu ,  Yeur-Luen Tu

IPC: H01L27/146 ,  H01L31/18

CPC classification number: H01L27/14614 ,  H01L27/14636 ,  H01L27/14643 ,  H01L27/14689 ,  H01L31/18

Abstract: In some embodiments, the present disclosure relates to a method of forming an integrated chip. The method is performed by forming a gate dielectric layer over a substrate, and selectively forming a gate material over the gate dielectric layer. A gate dielectric protection layer is formed over the gate dielectric layer, and a first sidewall spacer is formed over the gate dielectric protection layer and flanking a side of the gate material. The gate dielectric protection layer continuously extends from between the first sidewall spacer and the gate dielectric layer to outside of the first sidewall spacer.

公开(公告)号：US09659981B2

公开(公告)日：2017-05-23

申请号：US13743979

申请日：2013-01-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shyh-Fann Ting ,  Chih-Yu Lai ,  Cheng-Ta Wu ,  Yeur-Luen Tu ,  Ching-Chun Wang

IPC: H01L27/146

CPC classification number: H01L27/146 ,  H01L27/1463 ,  H01L27/1464 ,  H01L27/14683

Abstract: A semiconductor image sensor device having a negatively-charged layer includes a semiconductor substrate having a p-type region, a plurality of radiation-sensing regions in the p-type region proximate a front side of the semiconductor substrate, and a negatively-charged layer adjoining the p-type region proximate the plurality of radiation-sensing regions. The negatively-charged layer may be an oxygen-rich silicon oxide, a high-k metal oxide, or a silicon nitride formed as a liner in a shallow trench isolation feature, a sidewall spacer or an offset spacer of a transistor gate, a salicide-block layer, a buffer layer under a salicide-block layer, a backside surface layer, or a combination of these.

公开(公告)号：US09653507B2

公开(公告)日：2017-05-16

申请号：US14314193

申请日：2014-06-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Hsien Chou ,  Shih Pei Chou ,  Chih-Yu Lai ,  Sheng-Chau Chen ,  Chih-Ta Chen ,  Yeur-Luen Tu ,  Chia-Shiung Tsai

IPC: H01L27/146 ,  H01L33/20

CPC classification number: H01L27/14685 ,  H01L27/1462 ,  H01L27/1463 ,  H01L27/14687 ,  H01L33/20

Abstract: Some embodiments of the present disclosure relate to a deep trench isolation (DTI) structure configured to enhance efficiency and performance of a photovoltaic device. The photovoltaic device comprises a functional layer disposed over an upper surface of a semiconductor substrate, and a pair of pixels formed within the semiconductor substrate, which are separated by the DTI structure. The DTI structure is arranged within a deep trench. Sidewalls of the deep trench are partially covered with a protective sleeve formed along the functional layer prior to etching the deep trench. The protective sleeve prevents etching of the functional layer while etching the deep trench, which prevents contaminants from penetrating the pair of pixels. The protective sleeve also narrows the width of the DTI structure, which increases pixel area and subsequently the efficiency and performance of the photovoltaic device.

公开(公告)号：US09425343B2

公开(公告)日：2016-08-23

申请号：US14016996

申请日：2013-09-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Yu Lai ,  Cheng-Ta Wu ,  Yeur-Luen Tu ,  Chia-Shiung Tsai ,  Jhy-Jyi Sze ,  Shyh-Fann Ting ,  Ching-Chun Wang

IPC: H01L27/146 ,  H01L31/18

CPC classification number: H01L31/18 ,  H01L27/14614 ,  H01L27/14643

Abstract: Embodiments of mechanisms for forming an image sensor device are provided. The image sensor device includes a semiconductor substrate and one photodetector formed in the semiconductor substrate. The image sensor device also includes one gate stack formed over the semiconductor substrate. The gate stack includes multiple polysilicon layers.

Abstract translation: 提供了用于形成图像传感器装置的机构的实施例。 图像传感器装置包括形成在半导体衬底中的半导体衬底和一个光电检测器。 图像传感器装置还包括形成在半导体衬底上的一个栅叠层。 栅堆叠包括多个多晶硅层。

公开(公告)号：US12087801B2

公开(公告)日：2024-09-10

申请号：US17646765

申请日：2022-01-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Hsien Chou ,  Chih-Yu Lai ,  Shih Pei Chou ,  Yen-Ting Chiang ,  Hsiao-Hui Tseng ,  Min-Ying Tsai

IPC: H01L27/146 ,  H01L21/762 ,  H01L29/06

CPC classification number: H01L27/14687 ,  H01L21/76229 ,  H01L27/1463 ,  H01L29/0653

Abstract: A method includes performing an anisotropic etching on a semiconductor substrate to form a trench. The trench has vertical sidewalls and a rounded bottom connected to the vertical sidewalls. A damage removal step is performed to remove a surface layer of the semiconductor substrate, with the surface layer exposed to the trench. The rounded bottom of the trench is etched to form a slant straight bottom surface. The trench is filled to form a trench isolation region in the trench.

公开(公告)号：US10163947B2

公开(公告)日：2018-12-25

申请号：US15803995

申请日：2017-11-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Hsien Chou ,  Wen-I Hsu ,  Tsun-Kai Tsao ,  Chih-Yu Lai ,  Jiech-Fun Lu ,  Yeur-Luen Tu

IPC: H01L21/00 ,  H01L27/146 ,  H01L31/18

Abstract: In some embodiments, the present disclosure relates to a method of forming an integrated chip. The method is performed by forming a gate dielectric layer over a substrate, and selectively forming a gate material over the gate dielectric layer. A gate dielectric protection layer is formed over the gate dielectric layer, and a first sidewall spacer is formed over the gate dielectric protection layer and flanking a side of the gate material. The gate dielectric protection layer continuously extends from between the first sidewall spacer and the gate dielectric layer to outside of the first sidewall spacer.

公开(公告)号：US09812477B2

公开(公告)日：2017-11-07

申请号：US15169994

申请日：2016-06-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Hsien Chou ,  Wen-I Hsu ,  Tsun-Kai Tsao ,  Chih-Yu Lai ,  Jiech-Fun Lu ,  Yeur-Luen Tu

IPC: H01L31/062 ,  H01L31/113 ,  H01L27/146 ,  H01L31/18

CPC classification number: H01L27/14614 ,  H01L27/14636 ,  H01L27/14643 ,  H01L27/14689 ,  H01L31/18

Abstract: The present disclosure relates to a method the present disclosure relates to an integrated chip having an active pixel sensor with a gate dielectric protection layer that reduces damage to an underlying gate dielectric layer during fabrication, and an associated method of formation. In some embodiments, the integrated chip has a photodetector disposed within a substrate, and a gate structure located over the substrate. A gate dielectric protection layer is disposed over the substrate and extends from along a sidewall of the gate structure to a location overlying the photodetector. The gate dielectric protection layer has an upper surface that is vertically below an upper surface of the gate structure.

公开(公告)号：US20160276384A1

公开(公告)日：2016-09-22

申请号：US15169994

申请日：2016-06-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Hsien Chou ,  Wen-I Hsu ,  Tsun-Kai Tsao ,  Chih-Yu Lai ,  Jiech-Fun Lu ,  Yeur-Luen Tu

IPC: H01L27/146

CPC classification number: H01L27/14614 ,  H01L27/14636 ,  H01L27/14643 ,  H01L27/14689 ,  H01L31/18

Abstract: The present disclosure relates to a method the present disclosure relates to an integrated chip having an active pixel sensor with a gate dielectric protection layer that reduces damage to an underlying gate dielectric layer during fabrication, and an associated method of formation. In some embodiments, the integrated chip has a photodetector disposed within a substrate, and a gate structure located over the substrate. A gate dielectric protection layer is disposed over the substrate and extends from along a sidewall of the gate structure to a location overlying the photodetector. The gate dielectric protection layer has an upper surface that is vertically below an upper surface of the gate structure.

Abstract translation: 本公开涉及一种方法，本公开涉及具有有源像素传感器的集成芯片，该有源像素传感器具有栅极介电保护层，其在制造期间减少对下面的栅极电介质层的损坏，以及相关联的形成方法。 在一些实施例中，集成芯片具有设置在衬底内的光电检测器和位于衬底上方的栅极结构。 栅介质保护层设置在衬底上并且沿着栅极结构的侧壁延伸到覆盖光电检测器的位置。 栅极绝缘保护层具有垂直于栅极结构的上表面的上表面。

公开(公告)号：US09412781B2

公开(公告)日：2016-08-09

申请号：US14867070

申请日：2015-09-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Hsien Chou ,  Wen-I Hsu ,  Tsun-Kai Tsao ,  Chih-Yu Lai ,  Jiech-Fun Lu ,  Yeur-Luen Tu

IPC: H01L31/062 ,  H01L31/113 ,  H01L27/146 ,  H01L31/18

CPC classification number: H01L27/14614 ,  H01L27/14636 ,  H01L27/14643 ,  H01L27/14689 ,  H01L31/18

Abstract: The present disclosure relates to a method the present disclosure relates to an active pixel sensor having a gate dielectric protection layer that reduces damage to an underlying gate dielectric layer during fabrication, and an associated method of formation. In some embodiments, the active pixel sensor has a photodetector disposed within a semiconductor substrate. A transfer transistor having a first gate structure is located on a first gate dielectric layer disposed above the semiconductor substrate. A reset transistor having a second gate structure is located on the first gate dielectric layer. A gate dielectric protection layer is disposed onto the gate oxide at a position extending between the first gate structure and the second gate structure and over the photodetector. The gate dielectric protection layer protects the first gate dielectric layer from etching procedures during fabrication of the active pixel sensor.