公开(公告)号：US11158377B2

公开(公告)日：2021-10-26

申请号：US16952411

申请日：2020-11-19

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shih Kuang Yang ,  Ping-Cheng Li ,  Hung-Ling Shih ,  Po-Wei Liu ,  Wen-Tuo Huang ,  Yu-Ling Hsu ,  Yong-Shiuan Tsair ,  Chia-Sheng Lin

IPC分类号： G11C16/08 ,  H01L27/108 ,  G11C11/16 ,  H01L27/11521

摘要： Various embodiments of the present application are directed towards an integrated memory chip with an enhanced device-region layout for reduced leakage current and an enlarged word-line etch process window (e.g., enhanced word-line etch resiliency). In some embodiments, the integrated memory chip comprises a substrate, a control gate, a word line, and an isolation structure. The substrate comprises a first source/drain region. The control gate and the word line are on the substrate. The word line is between and borders the first source/drain region and the control gate and is elongated along a length of the word line. The isolation structure extends into the substrate and has a first isolation-structure sidewall. The first isolation-structure sidewall extends laterally along the length of the word line and underlies the word line.

公开(公告)号：US10943913B2

公开(公告)日：2021-03-09

申请号：US16364405

申请日：2019-03-26

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Wen-Tuo Huang ,  Ping-Cheng Li ,  Hung-Ling Shih ,  Po-Wei Liu ,  Yu-Ling Hsu ,  Yong-Shiuan Tsair ,  Chia-Sheng Lin ,  Shih Kuang Yang

IPC分类号： H01L27/11521 ,  H01L23/528 ,  H01L23/532 ,  H01L29/49 ,  H01L29/423 ,  H01L29/66 ,  H01L29/40 ,  H01L21/768 ,  H01L23/522 ,  H01L29/788 ,  H01L21/28

摘要： Various embodiments of the present application are directed towards an integrated memory chip comprising a memory array with a strap-cell architecture that reduces the number of distinct strap-cell types and that reduces strap-line density. In some embodiments, the memory array is limited to three distinct types of strap cells: a source line/erase gate (SLEG) strap cell; a control gate/word line (CGWL) strap cell; and a word-line strap cell. The small number of distinct strap-cell types simplifies design of the memory array and further simplifies design of a corresponding interconnect structure. Further, in some embodiments, the three distinct strap-cell types electrically couple word lines, erase gates, and control gates to corresponding strap lines in different metallization layers of an interconnect structure. By spreading the strap lines amongst different metallization layers, strap-line density is reduced.

公开(公告)号：US10680002B2

公开(公告)日：2020-06-09

申请号：US15981056

申请日：2018-05-16

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Hung-Ling Shih ,  Chieh-Fei Chiu ,  Po-Wei Liu ,  Wen-Tuo Huang ,  Yu-Ling Hsu ,  Yong-Shiuan Tsair ,  Shih Kuang Yang

IPC分类号： H01L21/311 ,  H01L27/11521 ,  H01L29/788 ,  H01L21/308 ,  H01L21/768 ,  H01L21/027 ,  H01L21/762 ,  H01L21/28

摘要： In some embodiments, a method for forming a semiconductor device is provided. The method includes forming a pad stack over a semiconductor substrate, where the pad stack includes a lower pad layer and an upper pad layer. An isolation structure having a pair of isolation segments separated in a first direction by the pad stack is formed in the semiconductor substrate. The upper pad is removed to form an opening, where the isolation segments respectively have opposing sidewalls in the opening that slant at a first angle. A first etch is performed that partially removes the lower pad layer and isolation segments in the opening so the opposing sidewalls slant at a second angle greater than the first angle. A second etch is performed to round the opposing sidewalls and remove the lower pad layer from the opening. A floating gate is formed in the opening.

公开(公告)号：US09252150B1

公开(公告)日：2016-02-02

申请号：US14445697

申请日：2014-07-29

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Hung-Ling Shih ,  Yong-Shiuan Tsair ,  Tsun-Kai Tsao ,  Po-Wei Liu ,  Wen-Tuo Huang ,  Yu-Ling Hsu

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/06 ,  H01L29/49 ,  H01L29/51 ,  H01L21/027 ,  H01L21/28 ,  H01L21/762 ,  H01L21/321

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/42324 ,  H01L29/4916 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66825

摘要： The present disclosure relates to a non-volatile memory cell structure, and an associated method. A non-volatile memory cell includes two transistors spaced apart from one another with floating gates connected together by a floating gate bridge. During the operation, the non-volatile memory cell is programmed and erased from one first transistor and read from the other second transistor. Since the floating gates of the two transistors are connected together and insulated from other ambient layers, stored charges can be controlled from the first transistor and affect a threshold of the second transistor.

摘要翻译： 本公开涉及非易失性存储器单元结构以及相关联的方法。 非易失性存储单元包括两个彼此间隔开的晶体管，浮置栅极通过浮栅连接在一起。 在操作期间，非易失性存储单元被编程并从一个第一晶体管擦除并从另一个第二晶体管读取。 由于两个晶体管的浮置栅极连接在一起并与其他环境层绝缘，所以可以从第一晶体管控制存储的电荷并影响第二晶体管的阈值。

公开(公告)号：US11127827B2

公开(公告)日：2021-09-21

申请号：US16248881

申请日：2019-01-16

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yu-Ling Hsu ,  Ping-Cheng Li ,  Hung-Ling Shih ,  Po-Wei Liu ,  Wen-Tuo Huang ,  Yong-Shiuan Tsair ,  Chia-Sheng Lin ,  Shih Kuang Yang

IPC分类号： H01L29/423 ,  H01L23/528 ,  H01L23/522 ,  H01L29/40 ,  H01L21/265 ,  H01L29/66 ,  H01L29/788 ,  H01L21/3213 ,  H01L21/28

摘要： Various embodiments of the present application are directed towards a control gate layout to improve an etch process window for word lines. In some embodiments, an integrated chip comprises a memory array, an erase gate, a word line, and a control gate. The memory array comprises a plurality of cells in a plurality of rows and a plurality of columns. The erase gate and the word line are elongated in parallel along a row of the memory array. The control gate is elongated along the row and is between and borders the erase gate and the word line. Further, the control gate has a pad region protruding towards the erase gate and the word line. Because the pad region protrudes towards the erase gate and the word line, a width of the pad region is spread between word-line and erase-gate sides of the control gate.

公开(公告)号：US20200098877A1

公开(公告)日：2020-03-26

申请号：US16248881

申请日：2019-01-16

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yu-Ling Hsu ,  Ping-Cheng Li ,  Hung-Ling Shih ,  Po-Wei Liu ,  Wen-Tuo Huang ,  Yong-Shiuan Tsair ,  Chia-Sheng Lin ,  Shih Kuang Yang

IPC分类号： H01L29/423 ,  H01L23/528 ,  H01L23/522 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/265 ,  H01L29/66 ,  H01L29/788 ,  H01L29/40

摘要： Various embodiments of the present application are directed towards a control gate layout to improve an etch process window for word lines. In some embodiments, an integrated chip comprises a memory array, an erase gate, a word line, and a control gate. The memory array comprises a plurality of cells in a plurality of rows and a plurality of columns. The erase gate and the word line are elongated in parallel along a row of the memory array. The control gate is elongated along the row and is between and borders the erase gate and the word line. Further, the control gate has a pad region protruding towards the erase gate and the word line. Because the pad region protrudes towards the erase gate and the word line, a width of the pad region is spread between word-line and erase-gate sides of the control gate.

公开(公告)号：US20190355731A1

公开(公告)日：2019-11-21

申请号：US15981056

申请日：2018-05-16

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Hung-Ling Shih ,  Chieh-Fei Chiu ,  Po-Wei Liu ,  Wen-Tuo Huang ,  Yu-Ling Hsu ,  Yong-Shiuan Tsair ,  Shih Kuang Yang

IPC分类号： H01L27/11521 ,  H01L29/788 ,  H01L21/28 ,  H01L21/762 ,  H01L21/768 ,  H01L21/027 ,  H01L21/308

摘要： In some embodiments, a method for forming a semiconductor device is provided. The method includes forming a pad stack over a semiconductor substrate, where the pad stack includes a lower pad layer and an upper pad layer. An isolation structure having a pair of isolation segments separated in a first direction by the pad stack is formed in the semiconductor substrate. The upper pad is removed to form an opening, where the isolation segments respectively have opposing sidewalls in the opening that slant at a first angle. A first etch is performed that partially removes the lower pad layer and isolation segments in the opening so the opposing sidewalls slant at a second angle greater than the first angle. A second etch is performed to round the opposing sidewalls and remove the lower pad layer from the opening. A floating gate is formed in the opening.

公开(公告)号：US10269818B2

公开(公告)日：2019-04-23

申请号：US15914485

申请日：2018-03-07

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Tsun-Kai Tsao ,  Hung-Ling Shih ,  Po-Wei Liu ,  Shun-Shing Yang ,  Wen-Tuo Huang ,  Yong-Shiuan Tsair ,  S.K. Yang

IPC分类号： H01L27/11529 ,  H01L21/28 ,  H01L21/3105 ,  H01L29/423 ,  H01L27/11521

摘要： A semiconductor device includes a non-volatile memory and a logic circuit. The non-volatile memory includes a stacked structure comprising a first insulating layer, a floating gate, a second insulating layer, a control gate and a third insulating layer stacked in this order from a substrate; an erase gate line; and a word line. The logic circuit includes a field effect transistor comprising a gate electrode. The word line includes a protrusion, and a height of the protrusion from the substrate is higher than a height of the erase gate line from the substrate. The word line and the gate electrode are formed of polysilicon.

公开(公告)号：US10269815B2

公开(公告)日：2019-04-23

申请号：US15498743

申请日：2017-04-27

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： ShihKuang Yang ,  Hung-Ling Shih ,  Chieh-Fei Chiu ,  Po-Wei Liu ,  Wen-Tuo Huang ,  Yu-Ling Hsu ,  Yong-Shiuan Tsair

IPC分类号： H01L21/04 ,  H01L27/11521 ,  H01L29/423 ,  H01L21/306 ,  H01L21/3065

摘要： A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate, a second dielectric layer disposed between the floating gate and the control gate, sidewall spacers disposed on opposing sides of a stacked structure including the floating gate, the second dielectric layer and the control gate, and an erase gate and a select gate disposed on sides of the stacked structure, respectively. An upper surface of the erase gate and one of the sidewall spacers in contact with the erase gate form an angle θ1 at a contact point of the upper surface of the erase gate and the one of the sidewall spacers, where 90°

公开(公告)号：US10204822B2

公开(公告)日：2019-02-12

申请号：US15884304

申请日：2018-01-30

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Cheng-Hsien Chou ,  Hung-Ling Shih ,  Tsun-Kai Tsao ,  Ming-Huei Shen ,  Kuo-Hwa Tzeng ,  Yeur-Luen Tu

IPC分类号： H01L21/02 ,  H01L21/762

摘要： In a method for fabricating a semiconductor device, a trench is etched in a semiconductor substrate having a top surface, and a lining oxide layer is formed conformal to the trench. A negatively-charged liner covering the lining oxide layer and conformal to the trench is formed. The trench is partially filled with a flowable oxide to a level below the top surface of the semiconductor substrate, and the flowable oxide in the trench is cured. The negatively-charged liner above the cured flowable oxide is optionally removed. A silicon oxide is deposited in the remaining portion of the trench, and a planarization process is performed to remove excess portions of the silicon oxide over the top surface of the semiconductor substrate.