公开(公告)号：US12033863B2

公开(公告)日：2024-07-09

申请号：US17572162

申请日：2022-01-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-Yu Lin ,  Yi-Ruei Jhan ,  Fang-Wei Lee ,  Li-Te Lin ,  Pinyen Lin ,  Tze-Chung Lin

IPC: H01L21/311 ,  C23C16/452 ,  H01L21/67 ,  H01L21/677

CPC classification number: H01L21/311 ,  C23C16/452 ,  H01L21/31116 ,  H01L21/67063 ,  H01L21/67069 ,  H01L21/67098 ,  H01L21/67103 ,  H01L21/67115 ,  H01L21/6719 ,  H01L21/67225 ,  H01L21/67248 ,  H01L21/67748

Abstract: The present disclosure provides a semiconductor fabrication apparatus. The semiconductor apparatus includes a processing chamber for etching; a substrate stage integrated in the processing chamber and being configured to secure a semiconductor wafer; a reflective mirror configured inside the processing chamber to reflect thermal energy from the heating mechanism toward the semiconductor wafer; and a heating mechanism embedded in the process chamber and is operable to perform a baking process to remove a by-product generated during the etching. The heating mechanism is integrated between the reflective mirror and a gas distribution plate of the processing chamber.

公开(公告)号：US11757021B2

公开(公告)日：2023-09-12

申请号：US16996781

申请日：2020-08-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yi-Ruei Jhan ,  Kuan-Ting Pan ,  Kuo-Cheng Chiang ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/306 ,  H01L21/308 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/66795 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/308 ,  H01L21/30604 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/78696

Abstract: The present disclosure provide a method for using a hard mask layer on a top surface of fin structures to form a fin-top mask layer. The fin-top mask layer can function as an etch stop for subsequent processes. Using the fin-top hard mask layer allows a thinner conformal dielectric layer to be used to protect semiconductor fins during the subsequent process, such as during etching of sacrificial gate electrode layer. Using a thinner conformal dielectric layer can reduce the pitch of fins, particularly for input/output devices.

公开(公告)号：US12205985B2

公开(公告)日：2025-01-21

申请号：US17480108

申请日：2021-09-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Ruei Jhan ,  Kuo-Cheng Chiang ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: A device includes a substrate, a first stack of semiconductor nanostructures vertically overlying the substrate, and a gate structure surrounding the semiconductor nanostructures and abutting an upper side and first and second lateral sides of the first stack. A first epitaxial region laterally abuts a third lateral side of the first stack, and a second epitaxial region laterally abuts a fourth lateral side of the first stack. A first inactive fin laterally abuts the first epitaxial region, and a second inactive fin laterally abuts the second epitaxial region and is physically separated from the first inactive fin by the gate structure.

公开(公告)号：US20240339526A1

公开(公告)日：2024-10-10

申请号：US18750379

申请日：2024-06-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Ting Pan ,  Huan-Chieh Su ,  Jia-Chuan You ,  Shi Ning Ju ,  Kuo-Cheng Chiang ,  Yi-Ruei Jhan ,  Li-Yang Chuang ,  Chih-Hao Wang

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/06

CPC classification number: H01L29/6681 ,  H01L21/823431 ,  H01L29/0649 ,  H01L29/0669

Abstract: A semiconductor structure includes a plurality of fin structures extending along a first direction, a plurality of gate structure segments positioned along a line extending in a second direction, the second direction being orthogonal to the first direction, wherein the gate structure segments are separated by dummy fin structures. The semiconductor structure further includes a conductive layer disposed over both the gate structure segments and the dummy fin structures to electrically connect at least some of the gate structure segments, and a cut feature aligned with one of the dummy fin structures and positioned to electrically isolate gate structure segments on both sides of the one of the dummy fin structures.

公开(公告)号：US20220344333A1

公开(公告)日：2022-10-27

申请号：US17476418

申请日：2021-09-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Ruei Jhan ,  Kuan-Ting Pan ,  Shi-Ning JU ,  Kuo-Cheng CHIANG ,  Chih-Hao WANG

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66

Abstract: A device includes a substrate, a first semiconductor channel over the substrate, a second semiconductor channel over the substrate and laterally offset from the first semiconductor channel, an isolation feature embedded in the substrate and laterally between the first and second semiconductor channels, a first liner layer laterally surrounding the isolation feature between the isolation feature and the first semiconductor channel, and a second liner layer laterally surrounding the first liner layer between the first liner layer and the first semiconductor channel.

公开(公告)号：US20210202247A1

公开(公告)日：2021-07-01

申请号：US17201744

申请日：2021-03-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Ruei Jhan ,  Han-Yu Lin ,  Li-Te Lin ,  Pinyen Lin

IPC: H01L21/02 ,  H01L29/66 ,  H01L29/40 ,  H01L21/3105 ,  H01L21/265

Abstract: A method includes forming a gate spacer on sidewalls of a dummy gate structure disposed over a semiconductor substrate; performing a first implantation process to the gate spacer, wherein the first implantation process includes bombarding an upper portion of the gate spacer with silicon atoms; after performing the first implantation process, performing a second implantation process to the upper portion of the gate spacer, where the second implantation process includes bombarding the upper portion of the gate spacer with carbon atoms; and after performing the second implantation process, replacing the dummy gate structure with a high-k metal gate structure, wherein the replacing includes forming an interlayer dielectric (ILD) layer.

公开(公告)号：US12021136B2

公开(公告)日：2024-06-25

申请号：US18361556

申请日：2023-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Ting Pan ,  Huan-Chieh Su ,  Jia-Chuan You ,  Shi Ning Ju ,  Kuo-Cheng Chiang ,  Yi-Ruei Jhan ,  Li-Yang Chuang ,  Chih-Hao Wang

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/06

CPC classification number: H01L29/6681 ,  H01L21/823431 ,  H01L29/0649 ,  H01L29/0669

Abstract: A semiconductor structure includes a plurality of fin structures extending along a first direction, a plurality of gate structure segments positioned along a line extending in a second direction, the second direction being orthogonal to the first direction, wherein the gate structure segments are separated by dummy fin structures. The semiconductor structure further includes a conductive layer disposed over both the gate structure segments and the dummy fin structures to electrically connect at least some of the gate structure segments, and a cut feature aligned with one of the dummy fin structures and positioned to electrically isolate gate structure segments on both sides of the one of the dummy fin structures.

公开(公告)号：US11908685B2

公开(公告)日：2024-02-20

申请号：US17201744

申请日：2021-03-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Ruei Jhan ,  Han-Yu Lin ,  Li-Te Lin ,  Pinyen Lin

IPC: H01L21/02 ,  H01L29/66 ,  H01L29/40 ,  H01L21/3105 ,  H01L21/265

CPC classification number: H01L21/02321 ,  H01L21/26586 ,  H01L21/31053 ,  H01L29/401 ,  H01L29/66545

Abstract: A method includes forming a gate spacer on sidewalls of a dummy gate structure disposed over a semiconductor substrate; performing a first implantation process to the gate spacer, wherein the first implantation process includes bombarding an upper portion of the gate spacer with silicon atoms; after performing the first implantation process, performing a second implantation process to the upper portion of the gate spacer, where the second implantation process includes bombarding the upper portion of the gate spacer with carbon atoms; and after performing the second implantation process, replacing the dummy gate structure with a high-k metal gate structure, wherein the replacing includes forming an interlayer dielectric (ILD) layer.

公开(公告)号：US11854908B2

公开(公告)日：2023-12-26

申请号：US17662569

申请日：2022-05-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Ting Pan ,  Huan-Chieh Su ,  Zhi-Chang Lin ,  Shi Ning Ju ,  Yi-Ruei Jhan ,  Kuo-Cheng Chiang ,  Chih-Hao Wang

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/311 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L21/823878 ,  H01L21/02603 ,  H01L21/31111 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L27/092 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66515 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66742 ,  H01L29/78603 ,  H01L29/78618 ,  H01L29/78696

Abstract: A method of fabricating a device includes forming a dummy gate over a plurality of fins. Thereafter, a first portion of the dummy gate is removed to form a first trench that exposes a first hybrid fin and a first part of a second hybrid fin. The method further includes filling the first trench with a dielectric material disposed over the first hybrid fin and over the first part of the second hybrid fin. Thereafter, a second portion of the dummy gate is removed to form a second trench and the second trench is filled with a metal layer. The method further includes etching-back the metal layer, where a first plane defined by a first top surface of the metal layer is disposed beneath a second plane defined by a second top surface of a second part of the second hybrid fin after the etching-back the metal layer.

公开(公告)号：US11621195B2

公开(公告)日：2023-04-04

申请号：US16856033

申请日：2020-04-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Ting Pan ,  Chih-Hao Wang ,  Kuo-Cheng Chiang ,  Yi-Bo Liao ,  Yi-Ruei Jhan

IPC: H01L21/8234 ,  H01L21/762 ,  H01L29/423

Abstract: A semiconductor device includes a semiconductor substrate, a first semiconductor stack, a second semiconductor stack, a first gate structure, and a second gate structure. The semiconductor substrate comprising a first device region and a second device region. The first semiconductor stack is located on the semiconductor substrate over the first device region, and has first channels. The second semiconductor stack is located on the semiconductor substrate over the second device region, and has second channels. A total number of the first channels is greater than a total number of the second channels. The first gate structure encloses the first semiconductor stack. The second gate structure encloses the second semiconductor stack.