公开(公告)号：US20230068619A1

公开(公告)日：2023-03-02

申请号：US17459788

申请日：2021-08-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jung-Hao Chang ,  Fo-Ju Lin ,  Fang-Wei Lee ,  Li-Te Lin ,  Pinyen Lin

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/786 ,  H01L21/311

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The method can include forming a fin structure over a substrate. The fin structure can include first and second sacrificial layers. The method can further include forming a recess structure in a first portion of the fin structure, selectively etching the first sacrificial layer of a second portion of the fin structure over the second sacrificial layer of the second portion of the fin structure, and forming an inner spacer layer over the etched first sacrificial layer with the second sacrificial layer of the second portion of the fin structure being exposed.

公开(公告)号：US20210391447A1

公开(公告)日：2021-12-16

申请号：US17458087

申请日：2021-08-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-Yu Lin ,  Chansyun David Yang ,  Tze-Chung Lin ,  Fang-Wei Lee ,  Fo-Ju Lin ,  Li-Te Lin ,  Pinyen Lin

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/311 ,  H01L29/06

Abstract: A method of fabricating a semiconductor device includes forming a channel member suspended above a substrate, depositing a dielectric material layer wrapping around the channel member, performing an oxidation treatment to a surface portion of the dielectric material layer, selectively etching the surface portion of the dielectric material layer to expose sidewalls of the channel member, performing a nitridation treatment to remaining portions of the dielectric material layer and the exposed sidewalls of the channel member, thereby forming a nitride passivation layer partially wrapping around the channel member. The method also includes repeating the steps of performing the oxidation treatment and selectively etching until top and bottom surfaces of the channel member are exposed, removing the nitride passivation layer from the channel member, and forming a gate structure wrapping around the channel member.

公开(公告)号：US12218219B2

公开(公告)日：2025-02-04

申请号：US17459788

申请日：2021-08-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jung-Hao Chang ,  Fo-Ju Lin ,  Fang-Wei Lee ,  Li-Te Lin ,  Pinyen Lin

IPC: H01L29/66 ,  H01L21/311 ,  H01L29/423 ,  H01L29/786

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The method can include forming a fin structure over a substrate. The fin structure can include first and second sacrificial layers. The method can further include forming a recess structure in a first portion of the fin structure, selectively etching the first sacrificial layer of a second portion of the fin structure over the second sacrificial layer of the second portion of the fin structure, and forming an inner spacer layer over the etched first sacrificial layer with the second sacrificial layer of the second portion of the fin structure being exposed.

公开(公告)号：US20250040238A1

公开(公告)日：2025-01-30

申请号：US18361152

申请日：2023-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Wei Lu ,  Kenichi Sano ,  Tze-Chung Lin ,  Fang-Wei Lee ,  Chia-Chien Kuang ,  Yi-Chen Lo ,  Fo-Ju Lin ,  Li-Te Lin ,  Pinyen Lin

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: In an embodiment, a device includes: lower semiconductor nanostructures including a first semiconductor material; a lower epitaxial source/drain region adjacent the lower semiconductor nanostructures, the lower epitaxial source/drain region having a first conductivity type; upper semiconductor nanostructures including a second semiconductor material, the second semiconductor material different from the first semiconductor material; and an upper epitaxial source/drain region adjacent the upper semiconductor nanostructures, the upper epitaxial source/drain region having a second conductivity type, the second conductivity type being opposite the first conductivity type.

公开(公告)号：US11830928B2

公开(公告)日：2023-11-28

申请号：US17458087

申请日：2021-08-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-Yu Lin ,  Chansyun David Yang ,  Tze-Chung Lin ,  Fang-Wei Lee ,  Fo-Ju Lin ,  Li-Te Lin ,  Pinyen Lin

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/311 ,  H01L29/06

CPC classification number: H01L29/66553 ,  H01L21/31116 ,  H01L29/0649 ,  H01L29/6681 ,  H01L29/66545 ,  H01L29/66818 ,  H01L29/7853

Abstract: A method of fabricating a semiconductor device includes forming a channel member suspended above a substrate, depositing a dielectric material layer wrapping around the channel member, performing an oxidation treatment to a surface portion of the dielectric material layer, selectively etching the surface portion of the dielectric material layer to expose sidewalls of the channel member, performing a nitridation treatment to remaining portions of the dielectric material layer and the exposed sidewalls of the channel member, thereby forming a nitride passivation layer partially wrapping around the channel member. The method also includes repeating the steps of performing the oxidation treatment and selectively etching until top and bottom surfaces of the channel member are exposed, removing the nitride passivation layer from the channel member, and forming a gate structure wrapping around the channel member.

公开(公告)号：US20230118700A1

公开(公告)日：2023-04-20

申请号：US18066354

申请日：2022-12-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-Yu Lin ,  Chansyun David Yang ,  Tze-Chung Lin ,  Fang-Wei Lee ,  Fo-Ju Lin ,  Li-Te Lin ,  Pinyen Lin

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/311 ,  H01L29/06

Abstract: A method for forming a semiconductor structure includes forming a fin on a semiconductor substrate. The fin includes channel layers and sacrificial layers stacked one on top of the other in an alternating fashion. The method also includes removing a portion of the fin to form a first opening and expose vertical sidewalls of the channel layers and the sacrificial layers, epitaxially growing a source/drain feature in the first opening from the exposed vertical sidewalls of the channel layers and the sacrificial layers, removing another portion of the fin to form a second opening to expose a vertical sidewall of the source/drain feature, depositing a dielectric layer in the second opening to cover the exposed vertical sidewall of the source/drain feature, and replacing the sacrificial layers with a metal gate structure in the second opening. The dielectric layer separates the source/drain feature from contacting the metal gate structure.

公开(公告)号：US11107904B2

公开(公告)日：2021-08-31

申请号：US16592281

申请日：2019-10-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-Yu Lin ,  Chansyun David Yang ,  Tze-Chung Lin ,  Fang-Wei Lee ,  Fo-Ju Lin ,  Li-Te Lin ,  Pinyen Lin

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/311 ,  H01L29/06

Abstract: A method of fabricating a semiconductor device includes forming a structure including multiple nanowires vertically stacked above a substrate; depositing a dielectric material layer wrapping around the nanowires; performing a treatment process to a surface portion of the dielectric material layer; selectively etching the surface portion of the dielectric material layer; repeating the steps of performing the treatment process and selectively etching until the nanowires are partially exposed; and forming a gate structure engaging the nanowires.