公开(公告)号：US11424341B2

公开(公告)日：2022-08-23

申请号：US16937901

申请日：2020-07-24

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yi-Chen Lo ,  Li-Te Lin ,  Pinyen Lin

IPC: H01L21/02 ,  H01L29/66 ,  H01L21/3065 ,  H01L21/033 ,  H01L21/027 ,  H01L29/423 ,  H01L21/308 ,  H01L21/768 ,  H01L29/78 ,  H01L21/321 ,  H01L21/311 ,  H01L21/3213

Abstract: A semiconductor device includes a substrate, a semiconductor fin, a gate electrode, a pair of gate spacers, a dielectric cap, and a hard mask layer. The semiconductor fin extends upwardly from the substrate. The gate electrode straddles the semiconductor fin. The pair of gate spacers is on opposite sidewalls of the gate electrode. The dielectric cap is atop the gate electrode and laterally between the pair of gate spacers. The hard mask layer is atop the dielectric cap and laterally between the pair of gate spacers. A bottommost position of the hard mask layer is not lower than a topmost position of the dielectric cap.

公开(公告)号：US11929424B2

公开(公告)日：2024-03-12

申请号：US17873962

申请日：2022-07-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yi-Chen Lo ,  Li-Te Lin ,  Pinyen Lin

IPC: H01L21/033 ,  H01L21/027 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/311 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/768 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66545 ,  H01L21/0274 ,  H01L21/0337 ,  H01L21/3065 ,  H01L21/3086 ,  H01L21/31122 ,  H01L21/3212 ,  H01L21/32136 ,  H01L21/76832 ,  H01L29/4236 ,  H01L29/66553 ,  H01L29/7851 ,  H01L29/7848

Abstract: A method includes forming a semiconductor fin on a substrate; forming a dielectric layer over the semiconductor fin; forming a metal gate electrode in the dielectric layer and extending across the semiconductor fin; forming a source/drain regions on the semiconductor fin and on opposite sides of the metal gate electrode; performing a first non-zero bias plasma etching process to the metal gate electrode; after performing the first non-zero bias plasma etching process, performing a first zero bias plasma etching process to the metal gate electrode.

公开(公告)号：US11522065B2

公开(公告)日：2022-12-06

申请号：US17207425

申请日：2021-03-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yi-Chen Lo ,  Jung-Hao Chang ,  Li-Te Lin ,  Pinyen Lin

IPC: H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/49 ,  H01L29/165 ,  H01L27/12 ,  H01L27/088 ,  H01L21/3065 ,  H01L21/02 ,  H01L21/28 ,  H01L21/67 ,  H01J37/00 ,  H01L21/8234 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/84

Abstract: A method includes following steps. First and second gate electrodes are formed over a substrate, with an ILD layer between the first and second gate electrodes. A first etch operation is performed to etch the first and second gate electrodes. A sacrificial layer is formed across the etched first and second gate electrodes and the ILD layer. A second etch operation is performed to etch the sacrificial layer and the etched the first and second gate electrodes.

公开(公告)号：US10957779B2

公开(公告)日：2021-03-23

申请号：US16158141

申请日：2018-10-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yi-Chen Lo ,  Jung-Hao Chang ,  Li-Te Lin ,  Pinyen Lin

IPC: H01L21/8234 ,  H01L21/3213 ,  H01L21/311 ,  H01L27/088 ,  H01L29/66 ,  H01L29/423 ,  H01L29/51 ,  H01J37/00 ,  H01L29/78 ,  H01L21/3065 ,  H01L21/02 ,  H01L21/28 ,  H01L21/67 ,  H01L29/49 ,  H01L21/84 ,  H01L29/165 ,  H01L27/12

Abstract: A method includes following steps. First and second gate electrodes are formed over a substrate, with an ILD layer between the first and second gate electrodes. A first etch operation is performed to etch the first and second gate electrodes. A sacrificial layer is formed across the etched first and second gate electrodes and the ILD layer. A second etch operation is performed to etch the sacrificial layer and the etched the first and second gate electrodes.

公开(公告)号：US10741671B2

公开(公告)日：2020-08-11

申请号：US16136339

申请日：2018-09-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yi-Chen Lo ,  Li-Te Lin ,  Pinyen Lin

IPC: H01L21/02 ,  H01L29/66 ,  H01L21/3065 ,  H01L21/033 ,  H01L21/027 ,  H01L29/423 ,  H01L21/308 ,  H01L21/768 ,  H01L29/78 ,  H01L21/321 ,  H01L21/311 ,  H01L21/3213

Abstract: A method for manufacturing a semiconductor device, includes: forming a dummy gate structure on a semiconductor substrate; forming a plurality of gate spacers on opposite sidewalls of the dummy gate structure; removing the dummy gate structure from the semiconductor substrate; forming a metal gate electrode on the semiconductor substrate and between the gate spacers; and performing a plasma etching process to the metal gate electrode, wherein the plasma etching process comprises performing in sequence a first non-zero bias etching step and a first zero bias etching step.

公开(公告)号：US11978640B2

公开(公告)日：2024-05-07

申请号：US17226332

申请日：2021-04-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yi-Chen Lo ,  Yi-Shan Chen ,  Chih-Kai Yang ,  Pinyen Lin

IPC: H01L21/311 ,  H01L21/033 ,  H01L21/66

CPC classification number: H01L21/31144 ,  H01L21/0337 ,  H01L22/12

Abstract: In a method of forming a pattern over a semiconductor substrate, a target layer to be patterned is formed over a substrate, a mask pattern including an opening is formed in a mask layer, a shifting film is formed in an inner sidewall of the opening, a one-directional etching operation is performed to remove a part of the shifting film and a part of the mask layer to form a shifted opening, and the target layer is patterned by using the mask layer with the shifted opening as an etching mask. A location of the shifted opening is laterally shifted from an original location of the opening.

公开(公告)号：US20230029651A1

公开(公告)日：2023-02-02

申请号：US17662284

申请日：2022-05-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Chen Lo

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/786

Abstract: The present disclosure describes a semiconductor device having a protection layer on inner spacer structures, The semiconductor device includes a nanostructure on a substrate. The nanostructure includes multiple semiconductor layers. The semiconductor device further includes a gate structure wrapped around a middle portion of the multiple semiconductor layers and a spacer structure adjacent to an end portion of the multiple semiconductor layers. The gate structure includes a high-k dielectric layer. The semiconductor device further includes a protection layer between the high-k dielectric layer and the spacer structure.

公开(公告)号：US11145749B2

公开(公告)日：2021-10-12

申请号：US16229979

申请日：2018-12-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yi-Chen Lo ,  Yu-Lien Huang ,  Li-Te Lin

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/768 ,  H01L29/423 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/04 ,  H01L29/45

Abstract: A method for fabricating a semiconductor device includes forming a gate electrode structure over a first region of a semiconductor substrate, and selectively forming an oxide layer overlying the gate electrode structure by reacting a halide compound with oxygen to increase a height of the gate electrode structure. The halide compound may be silicon tetrachloride, and the oxide layer may be silicon dioxide. The gate electrode structure may be a dummy gate electrode, which is subsequently removed, and replaced with another gate electrode structure.

公开(公告)号：US20240282569A1

公开(公告)日：2024-08-22

申请号：US18171508

申请日：2023-02-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Chen Lo ,  Ding-Kang Shih ,  Tsungyu Hung ,  Chia-Ling Pai ,  Pang-Yen Tsai ,  Li-Te Lin ,  Pinyen Lin

IPC: H01L21/02 ,  H01L21/768 ,  H01L21/8238 ,  H01L23/532 ,  H01L27/092 ,  H01L29/08 ,  H01L29/40 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L21/02068 ,  H01L21/76843 ,  H01L21/76861 ,  H01L21/823814 ,  H01L21/823871 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L27/092 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/66439 ,  H01L29/775 ,  H01L23/5226

Abstract: In an embodiment, a method includes forming a first semiconductor fin and a second semiconductor fin over a front-side of a substrate; etching a first recess in the first semiconductor fin and a second recess in the second semiconductor fin; forming a first epitaxial region in the first recess and first epitaxial nodules along sidewalls of the first recess; forming a second epitaxial region in the second recess and second epitaxial nodules along sidewalls of the second recess; flowing first precursors to remove the first epitaxial nodules; depositing an interlayer dielectric over the first epitaxial region and the second epitaxial region; etching a first opening in the interlayer dielectric to expose the first epitaxial region; forming a first epitaxial cap on the first epitaxial region and third epitaxial nodules over the interlayer dielectric; and flowing second precursors to remove the third epitaxial nodules.

公开(公告)号：US11843041B2

公开(公告)日：2023-12-12

申请号：US17856892

申请日：2022-07-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yi-Chen Lo ,  Jung-Hao Chang ,  Li-Te Lin ,  Pinyen Lin

IPC: H01L27/088 ,  H01L27/12 ,  H01L29/78 ,  H01L29/66 ,  H01L29/49 ,  H01L29/51 ,  H01L29/423 ,  H01L21/3065 ,  H01L21/02 ,  H01L21/28 ,  H01L21/67 ,  H01J37/00 ,  H01L21/8234 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/84 ,  H01L29/165

CPC classification number: H01L29/517 ,  H01J37/00 ,  H01L21/0228 ,  H01L21/02274 ,  H01L21/28088 ,  H01L21/3065 ,  H01L21/31122 ,  H01L21/32136 ,  H01L21/67069 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/42376 ,  H01L29/6681 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/785 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/7848

Abstract: A semiconductor device includes first and second gate structures over a substrate, the first gate structure has a first width that is smaller than a second width of the second gate structure, in which a lower portion of the first gate structure having a first work-function material (WFM) layer, the first WFM layer having a top surface, a lower portion of the second gate structure having a second WFM layer, the second WFM layer having a top surface. A first gate electrode is disposed over the first WFM layer and a second gate electrode has a lower portion disposed in the second WFM layer, in which the first gate electrode has a first width that is smaller than a second width of the second gate electrode, and wherein the top surface of the second WFM layer is at a level below a top surface of the second gate electrode.