公开(公告)号：US20130043547A1

公开(公告)日：2013-02-21

申请号：US13213863

申请日：2011-08-19

Applicant: Chia-Hua Chu ,  Chung-Hsien Lin

Inventor： Chia-Hua Chu ,  Chung-Hsien Lin

IPC: H01L27/20 ,  H01L21/98

CPC classification number: B81C1/00238 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81B2207/012 ,  H01L23/10 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/94 ,  H01L2224/02166 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/0362 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05558 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/05609 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/06181 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/1146 ,  H01L2224/11622 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13166 ,  H01L2224/16145 ,  H01L2224/73257 ,  H01L2224/81011 ,  H01L2224/81013 ,  H01L2224/81054 ,  H01L2224/81065 ,  H01L2224/81203 ,  H01L2224/81805 ,  H01L2224/8182 ,  H01L2224/94 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1437 ,  H01L2924/1461 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2924/014 ,  H01L2224/05552

Abstract: A method and device having chip scale MEMS packaging is described. A first substrate includes a MEMS device and a second substrate includes an integrated circuit. The frontside of the first substrate is bonded to the backside of the second substrate. Thus, the second substrate provides a cavity to encase, protect or operate the MEMS device within. The bond may provide an electrical connection between the first and second substrate. In an embodiment, a through silicon via is used to carry the signals from the first substrate to an I/O connection on the frontside of the second substrate.

Abstract translation: 描述了具有芯片级MEMS封装的方法和装置。 第一衬底包括MEMS器件，第二衬底包括集成电路。 第一衬底的前侧结合到第二衬底的背面。 因此，第二衬底提供了一个空腔来封装，保护或操作其中的MEMS器件。 该键可以在第一和第二衬底之间提供电连接。 在一个实施例中，穿通硅通孔用于将信号从第一衬底传送到第二衬底的前侧上的I / O连接。

公开(公告)号：US20120244665A1

公开(公告)日：2012-09-27

申请号：US13404521

申请日：2012-02-24

Applicant: Taiji SAKAI ,  Nobuhiro Imaizumi ,  Masataka Mizukoshi

Inventor： Taiji SAKAI ,  Nobuhiro Imaizumi ,  Masataka Mizukoshi

IPC: H01L21/60

CPC classification number: H01L24/81 ,  H01L24/11 ,  H01L24/13 ,  H01L24/75 ,  H01L2224/11013 ,  H01L2224/1184 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16225 ,  H01L2224/16245 ,  H01L2224/75101 ,  H01L2224/81065 ,  H01L2224/81075 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/8183 ,  H01L2224/83192 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/13064 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A method of manufacturing a semiconductor device includes: forming a first layer including crystals by processing a surface of a first electrode of a semiconductor element; forming a second layer including crystals by processing a surface of a second electrode of a mounting member on which the semiconductor element is mounted; reducing a first oxide film present over or in the first layer and a second oxide film present over or in the second layer at a first temperature, the first temperature being lower than a second temperature at which a first metal included in the first electrode diffuses in a solid state and being lower than a third temperature at which a second metal included in the second electrode diffuses in a solid state; and bonding the first layer and the second layer to each other by solid-phase diffusion.

Abstract translation: 一种制造半导体器件的方法包括：通过处理半导体元件的第一电极的表面，形成包括晶体的第一层; 通过加工其上安装有半导体元件的安装构件的第二电极的表面，形成包括晶体的第二层; 在第一温度下减少存在于第一层上或第一层中的第一氧化物膜和存在于第二层中或第二层中的第二氧化物膜，第一温度低于包含在第一电极中的第一金属扩散的第二温度 并且低于包含在第二电极中的第二金属以固态扩散的第三温度; 以及通过固相扩散将第一层和第二层彼此结合。

公开(公告)号：US20120193800A1

公开(公告)日：2012-08-02

申请号：US13313349

申请日：2011-12-07

Applicant: Toshiya Akamatsu ,  Nobuhiro Imaizumi ,  Seiki Sakuyama ,  Keisuke Uenishi ,  Tetsuhiro Nakanishi

Inventor： Toshiya Akamatsu ,  Nobuhiro Imaizumi ,  Seiki Sakuyama ,  Keisuke Uenishi ,  Tetsuhiro Nakanishi

IPC: H01L23/488 ,  H05K1/02 ,  C22C30/04 ,  B23K31/02 ,  C22C12/00 ,  C22C30/06

CPC classification number: H05K3/3463 ,  B23K35/0244 ,  B23K35/262 ,  B23K35/264 ,  B23K2101/36 ,  B23K2101/40 ,  C22C12/00 ,  C22C13/00 ,  C22C30/04 ,  C22C30/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16506 ,  H01L2224/81065 ,  H01L2224/81097 ,  H01L2224/81192 ,  H01L2224/81211 ,  H01L2224/81805 ,  H01L2224/81815 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/15311 ,  Y10T428/12708 ,  H01L2924/01083 ,  H01L2924/0105 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599

Abstract: A solder includes Sn (tin), Bi (bismuth) and Zn (zinc), wherein the solder has a Zn content of 0.01% by weight to 0.1% by weight.

Abstract translation: 焊料包括Sn（锡），Bi（铋）和Zn（锌），其中焊料的Zn含量为0.01重量％至0.1重量％。

公开(公告)号：US07879455B2

公开(公告)日：2011-02-01

申请号：US11633419

申请日：2006-12-05

Applicant: Ryoichi Kajiwara ,  Kazutoshi Itou

Inventor： Ryoichi Kajiwara ,  Kazutoshi Itou

IPC: H01L23/48 ,  B23K35/26 ,  C22C13/02

CPC classification number: C22C13/02 ,  B23K35/02 ,  B23K35/025 ,  B23K35/22 ,  B23K35/262 ,  B23K35/3006 ,  B23K35/302 ,  H01L23/49513 ,  H01L24/01 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/84 ,  H01L2224/0401 ,  H01L2224/05111 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/29101 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/29294 ,  H01L2224/29298 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/371 ,  H01L2224/37147 ,  H01L2224/37599 ,  H01L2224/376 ,  H01L2224/40091 ,  H01L2224/40225 ,  H01L2224/45124 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/48739 ,  H01L2224/48747 ,  H01L2224/4911 ,  H01L2224/73265 ,  H01L2224/81065 ,  H01L2224/81075 ,  H01L2224/81097 ,  H01L2224/81805 ,  H01L2224/83065 ,  H01L2224/83075 ,  H01L2224/83097 ,  H01L2224/83203 ,  H01L2224/83211 ,  H01L2224/83447 ,  H01L2224/83455 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01009 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01031 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/0133 ,  H01L2924/0134 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/20108 ,  H01L2924/30105 ,  H01L2924/351 ,  Y10T428/12528 ,  Y10T428/12708 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/01026 ,  H01L2924/3512 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299 ,  H01L2224/2929

Abstract: The present invention intends to provide a power semiconductor device using a high-temperature lead-free solder material, the high-temperature lead-free solder material having the heat resistant property at 280° C. or more, and the bondability at 400° C. or less, and excellent in the suppliabilty and wettability of solder, and in the high-temperature storage reliability and the temperature cycle reliability. In the power semiconductor device according to the present invention, a semiconductor element and a metal electrode member were bonded each other by a high-temperature solder material comprising Sn, Sb, Ag, and Cu as the main constitutive elements and the rest of other unavoidable impurity elements wherein the high-temperature solder material comprises 42 wt %≦Sb/(Sn+Sb)≦48 wt %, 5 wt %≦Ag

Abstract translation: 本发明旨在提供一种使用高温无铅焊料的功率半导体器件，具有280℃以上的耐热性的高温无铅焊料以及400℃下的结合性 或更低，焊料的可供应性和润湿性优异，以及高温存储的可靠性和温度循环的可靠性。 在根据本发明的功率半导体器件中，半导体元件和金属电极构件通过包含Sn，Sb，Ag和Cu的高温焊料作为主要构成元素彼此接合，而其余的不可避免的 杂质元素，其中高温焊料材料包含42重量％＆lt; Sb;（Sn + Sb）＆nlE; 48重量％，5重量％＆lt; NE; Ag <20重量％，3重量％＆lt; 和Ag + Cu＆nlE; 25wt％。

公开(公告)号：US20100291732A1

公开(公告)日：2010-11-18

申请号：US12805048

申请日：2010-07-08

Applicant: Yoichiro Kurita

Inventor： Yoichiro Kurita

IPC: H01L21/60 ,  B23K20/00 ,  B23K31/02

CPC classification number: B23K1/0016 ,  B23K2101/40 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/481 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/75 ,  H01L24/81 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05559 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13551 ,  H01L2224/13562 ,  H01L2224/1357 ,  H01L2224/13609 ,  H01L2224/13611 ,  H01L2224/16146 ,  H01L2224/16235 ,  H01L2224/27416 ,  H01L2224/27436 ,  H01L2224/27515 ,  H01L2224/27552 ,  H01L2224/2761 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/75251 ,  H01L2224/75252 ,  H01L2224/75314 ,  H01L2224/75745 ,  H01L2224/7598 ,  H01L2224/81048 ,  H01L2224/81065 ,  H01L2224/8109 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/8121 ,  H01L2224/81825 ,  H01L2224/8183 ,  H01L2224/81906 ,  H01L2224/81907 ,  H01L2224/83 ,  H01L2224/83102 ,  H01L2224/83191 ,  H01L2224/83862 ,  H01L2224/92 ,  H01L2224/92242 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/014 ,  H01L2924/01083 ,  H01L2924/0103 ,  H01L2924/01082 ,  H01L2224/81 ,  H01L2924/0665 ,  H01L2224/27 ,  H01L2224/11 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2224/16145 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2924/00012

Abstract: A manufacturing method for an electronic device joining a first metallic bond part formed on a first electronic component and a second metallic bond part formed on a second electronic component includes a first process for placing the first metallic bond part directly against the second metallic bond part, applying pressure to the first electronic component and the second electronic component, joining the first metallic bond part to the second metallic bond part with solid-phase diffusion, and releasing the applied pressure, and a second process for heating the first electronic component and the second electronic component at a predetermined temperature such that the first metallic bond part and the second metallic bond part are joined together by melting the first metallic bond part and the second metallic bond part.

Abstract translation: 接合形成在第一电子部件上的第一金属接合部和形成在第二电子部件上的第二金属接合部的电子设备的制造方法包括：将第一金属接合部直接放置在第二金属接合部上的第一工序， 向所述第一电子部件和所述第二电子部件施加压力，将所述第一金属接合部与所述第二金属接合部以固相扩散接合，释放所施加的压力，以及第二加工所述第一电子部件和所述第二电子部件 电子部件在预定温度下使得第一金属接合部分和第二金属接合部分通过熔化第一金属接合部分和第二金属接合部分而接合在一起。

公开(公告)号：US20230260953A1

公开(公告)日：2023-08-17

申请号：US18108725

申请日：2023-02-13

Applicant: Kulicke and Soffa Industries, Inc.

Inventor： Matthew B. Wasserman, JR. ,  Thomas J. Colosimo, JR.

IPC: H01L23/00 ,  B01D53/40

CPC classification number: H01L24/75 ,  B01D53/40 ,  H01L24/81 ,  H01L2224/751 ,  H01L2224/759 ,  B01D2258/0216 ,  H01L2224/81203 ,  H01L2224/81986 ,  H01L2224/81908 ,  H01L2224/81065 ,  H01L2924/40

Abstract: A method of monitoring gas byproducts of a bonding system is provided. The method includes: providing a plurality of bonding systems, each of the bonding systems including a reducing gas delivery system for use in connection with a bonding operation, each of the bonding systems being configured for exhausting gas byproducts; connecting each of the bonding systems to a monitoring device using a respective gas delivery path; and monitoring a composition of at least a portion of the gas byproducts with the monitoring device.

公开(公告)号：US20180261574A1

公开(公告)日：2018-09-13

申请号：US15694838

申请日：2017-09-03

Applicant: Toshiba Memory Corporation

Inventor： Yuji KARAKANE ,  Masatoshi FUKUDA ,  Soichi HOMMA ,  Masayuki MIURA ,  Naoyuki KOMUTA ,  Yuka AKAHANE ,  Yukifumi OYAMA

IPC: H01L25/065 ,  H01L23/498 ,  H01L23/29 ,  H01L25/00 ,  H01L23/00 ,  H01L21/56 ,  H01L21/683

CPC classification number: H01L25/0657 ,  H01L21/565 ,  H01L21/6836 ,  H01L21/76897 ,  H01L23/293 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/50 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13118 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/1319 ,  H01L2224/1415 ,  H01L2224/1416 ,  H01L2224/16113 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/1703 ,  H01L2224/17051 ,  H01L2224/17181 ,  H01L2224/17505 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/81005 ,  H01L2224/81065 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81815 ,  H01L2224/8185 ,  H01L2224/83005 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/9211 ,  H01L2224/9212 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06565 ,  H01L2225/06586 ,  H01L2924/0635 ,  H01L2924/0665 ,  H01L2924/1438 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A semiconductor device includes a wiring substrate having a first surface, a stacked body on the first surface, the stacked body comprising a first chip, a second chip having a through via and positioned between the first chip and the first surface, and a third chip, a first resin contacting the first surface and the third chip, and a second resin sealing the stacked body. The first and second resins are made of different materials.

公开(公告)号：US09679875B2

公开(公告)日：2017-06-13

申请号：US15135599

申请日：2016-04-22

Applicant: International Business Machines Corporation

Inventor： Peter A. Gruber ,  Katsuyuki Sakuma ,  Da-Yuan Shih

IPC: H01L25/00 ,  H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L25/0657 ,  H01L21/565 ,  H01L23/3107 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/50 ,  H01L2224/0381 ,  H01L2224/0401 ,  H01L2224/05147 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/0612 ,  H01L2224/065 ,  H01L2224/11003 ,  H01L2224/11334 ,  H01L2224/1141 ,  H01L2224/1144 ,  H01L2224/11849 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/14104 ,  H01L2224/16012 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/16503 ,  H01L2224/17181 ,  H01L2224/73204 ,  H01L2224/81022 ,  H01L2224/81065 ,  H01L2224/8109 ,  H01L2224/811 ,  H01L2224/8112 ,  H01L2224/81201 ,  H01L2224/8121 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/8181 ,  H01L2224/81815 ,  H01L2224/81986 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/381 ,  H01L2924/3841 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/81203 ,  H01L2924/01047 ,  H01L2924/01029

Abstract: A method of forming a reduced volume interconnect for a chip stack including multiple silicon layers, the method including: forming multiple conductive structures, each of at least a subset of the conductive structures having a volume of conductive material for a corresponding under bump metallurgy pad onto which the conductive structure is transferred that is configured such that a ratio of an unreflowed diameter of the conductive structure to a diameter of the corresponding pad is about one third-to-one or less; transferring the conductive structures to the silicon layers; stacking the silicon layers in a substantially vertical dimension such that each of the conductive structures on a given silicon layer is aligned with a corresponding electrical contact location on an underside of an adjacent silicon layer; and heating the interconnect so as to metallurgically bond multiple electrical contact locations of adjacent silicon layers.

公开(公告)号：US20160268232A1

公开(公告)日：2016-09-15

申请号：US14839676

申请日：2015-08-28

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Yoichiro KURITA

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/31 ,  H01L21/48 ,  H01L25/00 ,  H01L23/498

CPC classification number: H01L25/0657 ,  H01L21/4853 ,  H01L21/56 ,  H01L21/561 ,  H01L23/3135 ,  H01L23/3157 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/562 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L24/97 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81065 ,  H01L2224/81815 ,  H01L2224/83005 ,  H01L2224/92125 ,  H01L2224/92225 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/10253 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1438 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2224/81 ,  H01L2924/00

Abstract: According to one embodiment, a semiconductor device includes a laminate including a plurality of semiconductor chips and having a first width, at least part of the semiconductor chips including an electrode extending through the semiconductor chip, the semiconductor chips being stacked and connected to each other via the electrode; a silicon substrate provided on a first surface of the laminate and having a second width larger than the first width; a wiring layer provided on a second surface of the laminate; and a resin provided around the laminate.

Abstract translation: 根据一个实施例，半导体器件包括包括多个半导体芯片并且具有第一宽度的层压体，至少部分半导体芯片包括延伸穿过半导体芯片的电极，半导体芯片被堆叠并彼此连接通过 电极; 设置在所述层压体的第一表面上并且具有大于所述第一宽度的第二宽度的硅基板; 设置在所述层叠体的第二面上的布线层; 以及设置在层叠体周围的树脂。

公开(公告)号：US09443820B2

公开(公告)日：2016-09-13

申请号：US14387380

申请日：2012-05-30

Applicant: Bernhard Rebhan

Inventor： Bernhard Rebhan

IPC: B23K37/00 ,  B23K37/04 ,  H01L23/00 ,  H01L21/67 ,  B23K20/14 ,  B23K20/24 ,  B23K20/26 ,  B23K31/02

CPC classification number: H01L24/75 ,  B23K20/14 ,  B23K20/24 ,  B23K20/26 ,  B23K31/02 ,  B23K37/00 ,  H01L21/67092 ,  H01L2224/751 ,  H01L2224/7525 ,  H01L2224/757 ,  H01L2224/758 ,  H01L2224/81065 ,  H01L2224/83065 ,  H01L2224/94 ,  H01L2924/1461 ,  H01L2224/81 ,  H01L2924/00

Abstract: A device for bonding of one bond side of a first substrate to one bond side of a second substrate, the device having one module group with a common working space which can be closed especially gastight to the environment, at least one bond module is connected in a sealed manner to the working space, and a movement apparatus for moving the first and second substrate in the working space.The module group has a reduction module which is connected, in a sealed manner to the working space for reducing the bond sides.

Abstract translation: 模块组具有减小模块，其以密封的方式连接到用于减少粘合侧的工作空间。