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公开(公告)号：US20230402392A1
公开(公告)日：2023-12-14
申请号：US18250128
申请日：2021-08-27
发明人： Huilong ZHU
IPC分类号： H01L23/538 , H01L29/423 , H01L29/06 , H01L29/786 , H01L29/775 , H01L27/092 , H01L21/8238
CPC分类号： H01L23/5386 , H01L29/42392 , H01L23/5383 , H01L29/0673 , H01L29/78696 , H01L29/775 , H01L27/092 , H01L21/823807 , H01L21/823871 , H01L21/823814
摘要： Disclosed are a semiconductor apparatus with a sidewall interconnection structure, a method of manufacturing the semiconductor apparatus, and an electronic device. The semiconductor apparatus includes: a plurality of device stacks, wherein each device stack includes a plurality of semiconductor devices stacked, and each semiconductor device includes a first source/drain layer, a channel layer, and a second source/drain layer stacked in a vertical direction, and a gate electrode surrounding the channel layer; and an interconnection structure between the plurality of device stacks. The interconnection structure includes: an electrical isolation layer; and a conductive structure in the electrical isolation layer. At least one of the first source/drain layer, the second source/drain layer, and the gate electrode of each of at least one of the semiconductor devices is in contact with and thus electrically connected to the conductive structure at a corresponding height in the interconnection structure in a lateral direction.
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公开(公告)号：US11827988B2
公开(公告)日：2023-11-28
申请号：US17891025
申请日：2022-08-18
发明人： Huilong Zhu , Xiaogen Yin , Chen Li , Anyan Du , Yongkui Zhang
IPC分类号： C23F1/16 , H01L21/306
CPC分类号： C23F1/16 , H01L21/30604
摘要： An embodiment of the present disclosure provides an etching method, having the following steps: forming a modified layer having a thickness of one or several atom layers on a selected region of a surface of a semiconductor material layer by using a modifier; and removing the modified layer. When a semiconductor is processed, this method achieves precise control over the etching thickness and improves the etching rate at the same time.
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133.发明公开公开(公告)号：US20230369489A1
公开(公告)日：2023-11-16
申请号：US18317722
申请日：2023-05-15
发明人： Huilong ZHU
IPC分类号： H01L29/78 , H01L21/225 , H01L29/06 , H01L29/423 , H01L29/786 , H01L23/522 , H01L29/66 , H01L21/8238 , H01L21/3065 , H01L21/223 , H01L27/092
CPC分类号： H01L29/7848 , H01L21/2253 , H01L29/0653 , H01L29/42392 , H01L29/78642 , H01L29/78696 , H01L29/78618 , H01L23/5221 , H01L29/66545 , H01L21/823885 , H01L21/823807 , H01L21/823878 , H01L21/3065 , H01L21/2236 , H01L27/0925 , H01L29/7827 , H01L29/66666 , H01L27/092 , H01L21/823828 , H01L21/823814 , H01L21/823871
摘要： There are provided a semiconductor device, a method of manufacturing the same, and an electronic device including the device. According to an embodiment, the semiconductor device may include a substrate, and a first device and a second device formed on the substrate. Each of the first device and the second device includes a first source/drain layer, a channel layer and a second source/drain layer stacked on the substrate in sequence, and also a gate stack surrounding a periphery of the channel layer. The channel layer of the first device and the channel layer of the second device are substantially co-planar.
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公开(公告)号：US20230368838A1
公开(公告)日：2023-11-16
申请号：US18247213
申请日：2021-01-25
发明人： Xiaoxin Xu , Jie Yu , Danian Dong , Zhaoan Yu , Hangbing Lv
IPC分类号： G11C13/00
CPC分类号： G11C13/0069 , G11C13/0064 , G11C13/0023 , G11C2013/0066
摘要： The memory circuit structure includes: a storage array, wherein the storage array includes at least two storage units; a decoder connected with a bit line and a word line of the storage array respectively; a programming circuit configured to generate a voltage pulse or a constant current pulse; a polarity switching circuit connected with the programming circuit, and configured to implement a switching between a voltage programming and a current programming of the programming circuit under a set operation and a reset operation; a detection circuit connected with the storage array, and configured to detect a detection signal of a current or a voltage corresponding to the specific storage unit in the storage array and feed back the detection signal to a control unit, wherein the detection signal output by the detection circuit is configured to enable the polarity switching circuit to switch; and the control unit.
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公开(公告)号：US11817480B2
公开(公告)日：2023-11-14
申请号：US17112343
申请日：2020-12-04
发明人： Huilong Zhu
IPC分类号： H01L29/06 , H01L29/41 , H01L29/423 , H01L27/092 , H01L29/10 , H01L29/78 , H01L21/8234 , H01L21/8238
CPC分类号： H01L29/1033 , H01L27/092 , H01L29/42356 , H01L29/7802 , H01L21/823412 , H01L21/823807 , H01L21/823885
摘要： A semiconductor device with U-shaped channel and electronic apparatus including the same are disclosed. the semiconductor device includes a first device and a second device opposite to each other on a substrate. The two devices each include: a channel portion vertically extending on the substrate and having a U-shape in a plan view; source/drain portions respectively located at upper and lower ends of the channel portion and along the U-shaped channel portion; and a gate stack overlapping the channel portion on an inner side of the U-shape. An opening of the U-shape of the first device and an opening of the U-shape of the second device are opposite to each other. At least a portion of the gate stack of the first device close to the channel portion and at least a portion of the gate stack of the second device close to the channel portion are substantially coplanar.
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公开(公告)号：US11776607B2
公开(公告)日：2023-10-03
申请号：US17424998
申请日：2019-01-28
发明人： Hangbing Lv , Qing Luo , Xiaoxin Xu , Tiancheng Gong , Ming Liu
CPC分类号： G11C11/223 , G06N3/063 , H01L29/516 , H01L29/78391 , H10B51/20 , H10B51/30
摘要： The present disclosure provides a fusion memory including a plurality of memory cells, wherein each memory cell of the plurality of memory cells includes: a bulk substrate; a source and a drain on the bulk substrate; a channel extending between the source and the drain; a ferroelectric layer on the channel; and a gate on the ferroelectric layer.
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公开(公告)号：US20230280978A1
公开(公告)日：2023-09-07
申请号：US18005756
申请日：2021-01-21
发明人： Guozhong XING , Huai LIN , Di WANG , Long LIU , Feng ZHANG , Changqing XIE , Ling LI , Ming LIU
CPC分类号： G06F7/57 , G11C11/161 , G11C11/1659 , G11C11/1673 , G11C11/1675
摘要： Provided are a spin orbit torque magnetic random access memory cell, a spin orbit torque magnetic random access memory array and a method for calculating a Hamming distance, wherein the spin orbit torque magnetic random access memory cell includes a magnetic tunnel junction; a first transistor, a drain terminal of the first transistor being connected to a bottom of the magnetic tunnel junction; and a second transistor, a drain terminal of the second transistor being connected to a top of the magnetic tunnel junction.
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公开(公告)号：US20230267990A1
公开(公告)日：2023-08-24
申请号：US18005101
申请日：2020-08-24
发明人： Qing LUO , Bing CHEN , Hangbing LV , Ming LIU , Cheng LU
IPC分类号： G11C11/4096 , G11C11/408 , G11C11/4094 , H03K19/017
CPC分类号： G11C11/4096 , G11C11/4085 , G11C11/4094 , H03K19/01742
摘要： Provided are a symmetric memory cell and a BNN circuit. The symmetric memory cell includes a first complementary structure and a second complementary structure, the second complementary structure being symmetrically connected to the first complementary structure in a first direction, wherein the first complementary structure includes a first control transistor configured to be connected to the second complementary structure, the second complementary structure includes a second control transistor, a drain electrode of the second control transistor and a drain electrode of the first control transistor being symmetrically arranged in the first direction and connected to a bit line, and the symmetric memory cell is configured to store a weight value 1 or 0.
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139.发明公开公开(公告)号：US20230253316A1
公开(公告)日：2023-08-10
申请号：US18300719
申请日：2023-04-14
发明人： Huilong Zhu
IPC分类号： H01L23/528 , H01L21/768 , H01L23/522
CPC分类号： H01L23/528 , H01L21/7682 , H01L21/7685 , H01L21/76801 , H01L21/76885 , H01L23/5226 , H01L23/53209
摘要： A metallization stack is provided. The metallization stack may include at least one interconnection line layer and at least one via hole layer arranged alternately on a substrate. At least one pair of adjacent interconnection line layer and via hole layer in the metallization stack includes an interconnection line in the interconnection line layer; and a via hole in the via hole layer. The via hole layer is arranged closer to the substrate than the interconnection line layer, and at least part of the interconnection line extends longitudinally in a first direction, and a sidewall of the at least part of the interconnection line in the first direction is substantially coplanar with at least upper portion of a corresponding sidewall of the via hole under the at least part of the interconnection line.
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公开(公告)号：US20230245691A1
公开(公告)日：2023-08-03
申请号：US18004968
申请日：2020-07-20
CPC分类号： G11C11/161 , H10B61/22 , H10N50/20 , H10N50/80 , H10N50/85 , H10N50/01 , G11C11/1659 , G11C11/1673 , G11C11/1675
摘要： Provided is a cache memory, including: a first field-effect transistor, a field-like spin torque layer underneath a magnetic tunnel junction, an electrode, and a second field-effect transistor sequentially arranged and connected; wherein the first field-effect transistor is configured to provide a writing current and to control the on-off of the writing current through a gate electrode; the field-like spin torque layer is configured to generate field-like spin torques for switching a first ferromagnetic layer of the magnetic tunnel junction; the magnetic tunnel junction includes a first ferromagnetic layer, a tunneling layer, a second ferromagnetic layer and a pinning layer arranged sequentially; the electrode is configured to connect the cache memory with the second field-effect transistor; and the second field-effect transistor is configured to control the on-off of the second field-effect transistor through the gate electrode to read the resistive state of the magnetic tunnel junction.
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