公开(公告)号：US20240321865A1

公开(公告)日：2024-09-26

申请号：US18590804

申请日：2024-02-28

申请人： Kioxia Corporation

发明人： Syunsuke SASAKI ,  Shouichi OZAKI ,  Kenichi SUGAWARA ,  Hiroaki NAKASA ,  Takeshi MIYABA ,  Maya OHSAKA ,  Shoki ITO

IPC分类号： H01L27/02 ,  H01L27/092 ,  H01L29/06 ,  H10B43/35 ,  H10B43/40

CPC分类号： H01L27/0266 ,  H01L27/0292 ,  H01L27/0925 ,  H01L29/0619 ,  H10B43/35 ,  H10B43/40

摘要： A semiconductor device includes a first pad to which a high voltage is to be input, a second pad to which a low voltage is to be input, a third pad to which a ground voltage is to be input, and a protection circuit provided between the first pad and the third pad. The protection circuit includes a first protection element group including a plurality of first transistors arranged in a first direction, a second protection element group including a plurality of second transistors arranged in the first direction and disposed apart from the first protection element group in a second direction orthogonal to the first direction, a guard ring provided around the first and second protection element groups, and an intermediate guard ring provided between the first protection element group and the second protection element group and connected to the third pad via a resistance element.

公开(公告)号：US11990475B2

公开(公告)日：2024-05-21

申请号：US17536413

申请日：2021-11-29

申请人： Samsung Electronics Co., Ltd.

发明人： Ahreum Kim ,  Sunghoon Kim ,  Daeseok Byeon

IPC分类号： H01L27/092 ,  H01L21/8238 ,  H01L27/02 ,  H01L25/065

CPC分类号： H01L27/0922 ,  H01L21/823814 ,  H01L21/823892 ,  H01L27/0207 ,  H01L27/092 ,  H01L27/0925 ,  H01L25/0657 ,  H01L2225/06524

摘要： A semiconductor device includes a substrate, an N-well area formed in the substrate, a first P-channel metal oxide semiconductor (PMOS) transistor having active regions formed in the N-well area, and a first N-channel metal oxide semiconductor (NMOS) transistor having active regions formed in the substrate. The first NMOS transistor includes a first N-type active region overlapping each of the substrate and the N-well area, when viewed from above a plane parallel to a top surface of the substrate.

公开(公告)号：US20240021483A1

公开(公告)日：2024-01-18

申请号：US18477004

申请日：2023-09-28

申请人： Institute of Microelectronics, Chinese Academy of Sciences

发明人： Huilong ZHU ,  Yongkui ZHANG ,  Xiaogen YIN ,  Chen LI ,  Yongbo LIU ,  Kunpeng JIA

IPC分类号： H01L21/8238 ,  H01L27/092

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/823885 ,  H01L27/0925 ,  H01L21/823842

摘要： The disclosed technology provides a semiconductor device, a manufacturing method thereof, and an electronic device including the device. An example semiconductor device includes a substrate; a first device and a second device on the substrate. Each of the first device and the second device include a first source/drain layer, a channel layer, and a second source layer that are sequentially stacked, from bottom to top, on the substrate, and a gate stack around at least a part of an outer periphery of the channel layer, with sidewalls of the respective channel layers of the first device and the second device extending at least partially along different crystal planes or crystal plane families.

公开(公告)号：US20180240815A1

公开(公告)日：2018-08-23

申请号：US15953960

申请日：2018-04-16

申请人： Horacio Mendez ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Terence B. HOOK ,  Horacio MENDEZ

IPC分类号： H01L27/12 ,  H01L21/265 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/84 ,  H01L21/326 ,  H01L29/36

CPC分类号： H01L27/1203 ,  H01L21/2652 ,  H01L21/326 ,  H01L21/823493 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/0925 ,  H01L29/0649 ,  H01L29/36

摘要： A fully-depleted silicon-on-insulator (FDSOI) semiconductor structure includes: a first PFET, a second PFET, and a third PFET each having a different threshold voltage and each being over an n-well that is biased to a first voltage; and a first NFET, a second NFET, and a third NFET each having a different threshold voltage and each being over a p-type substrate that is biased to a second voltage. The second voltage is different than the first voltage.

公开(公告)号：US09984939B2

公开(公告)日：2018-05-29

申请号：US15283239

申请日：2016-09-30

申请人： Semiconductor Manufacturing International (Beijing) Corporation ,  Semiconductor Manufacturing International (Shanghai) Corporation

发明人： Fei Zhou

IPC分类号： H01L21/76 ,  H01L21/8238 ,  H01L21/265 ,  H01L21/8234 ,  H01L27/092 ,  H01L29/66

CPC分类号： H01L21/823892 ,  H01L21/26513 ,  H01L21/823493 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0925 ,  H01L27/0927 ,  H01L27/0928 ,  H01L29/66803

摘要： A method for manufacturing a semiconductor device includes providing a substrate, performing an N-type dopant implantation into a first region of the substrate to form an N-well, removing a portion of the substrate to form a first set of fins on the N-well and a second set of fins on a second region of the substrate adjacent the N-well, filling gap spaces between the fins to form an isolation region, and performing a P-type dopant implantation into the second region to form a P-well adjacent the N-well. The N-well and the P-well are formed separately at different times. The loss of the P-type dopant ions due to the diffusion of P-type dopant ions in the P-well into the isolation region can be eliminated, and the damage to the fins caused by N-type dopant ions can be avoided.

公开(公告)号：US09953980B2

公开(公告)日：2018-04-24

申请号：US15329433

申请日：2014-09-29

申请人： MITSUBISHI ELECTRIC CORPORATION

发明人： Takayuki Nakai

IPC分类号： H03F3/26 ,  H01L27/092 ,  H03F3/45 ,  H03F3/30

CPC分类号： H01L27/0928 ,  H01L21/823892 ,  H01L27/092 ,  H01L27/0925 ,  H01L27/0927 ,  H03F3/3013 ,  H03F3/3018 ,  H03F3/45183 ,  H03F3/45224 ,  H03F2203/30006 ,  H03F2203/45006 ,  H03F2203/45281

摘要： In an output amplifier stage of an operational amplifier circuit, the first p-well of the first nMOSFET and the second p-well of the second nMOSFET are connected to the fourth node. Further, the first n-well of the first pMOSFET and the second n-well of the second pMOSFET are connected to the fifth node. At least one of the fourth node and the fifth node is connected to an output terminal VOUT.

公开(公告)号：US09543437B2

公开(公告)日：2017-01-10

申请号：US14863249

申请日：2015-09-23

申请人： Texas Instruments Incorporated

发明人： Youn Sung Choi ,  Greg Charles Baldwin

IPC分类号： H01L21/00 ,  H01L29/78 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/092 ,  H01L29/06 ,  H01L29/10

CPC分类号： H01L27/0207 ,  H01L21/823807 ,  H01L27/0203 ,  H01L27/092 ,  H01L27/0925 ,  H01L29/0638 ,  H01L29/1033 ,  H01L29/7843

摘要： An integrated circuit with DSL borders perpendicular to the transistor gates primarily inside the nwell and with DSL borders parallel to the transistor gates primarily outside the nwell. A method for forming an integrated circuit with DSL borders perpendicular to the transistor gates primarily inside the nwell and with DSL borders parallel to the transistor gates primarily outside the nwell.

摘要翻译： 主要在nwell内的垂直于晶体管栅极的DSL边界的集成电路，并且主要在nwell外部平行于晶体管栅极的DSL边界。 一种用于形成集成电路的方法，该集成电路具有垂直于晶体管栅极的DSL边界，主要在nwell内部，并且DSL边界平行于晶体管栅极主要在nwell外部。

公开(公告)号：US09484270B2

公开(公告)日：2016-11-01

申请号：US14487421

申请日：2014-09-16

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION ,  Horacio Mendez

发明人： Terence B. Hook ,  Horacio Mendez

IPC分类号： H01L27/12 ,  H01L29/74 ,  H01L29/788 ,  H01L29/66 ,  H01L21/84 ,  H01L27/092 ,  H01L21/326 ,  H01L21/8234 ,  H01L29/36 ,  H01L29/06 ,  H01L21/8238 ,  H01L21/265

CPC分类号： H01L27/1203 ,  H01L21/2652 ,  H01L21/326 ,  H01L21/823493 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/0925 ,  H01L29/0649 ,  H01L29/36

摘要： A fully-depleted silicon-on-insulator (FDSOI) semiconductor structure includes: a first PFET, a second PFET, and a third PFET each having a different threshold voltage and each being over an n-well that is biased to a first voltage; and a first NFET, a second NFET, and a third NFET each having a different threshold voltage and each being over a p-type substrate that is biased to a second voltage. The second voltage is different than the first voltage.

公开(公告)号：US09368500B2

公开(公告)日：2016-06-14

申请号：US14071670

申请日：2013-11-05

申请人： UNITED MICROELECTRONICS CORP.

发明人： Chang-Tzu Wang ,  Yu-Chun Chen ,  Tien-Hao Tang ,  Kuan-Cheng Su

IPC分类号： H01L27/092 ,  H01L29/78 ,  H01L27/06 ,  H01L27/02 ,  H01L21/8238

CPC分类号： H01L27/0925 ,  H01L21/823892 ,  H01L27/0274 ,  H01L27/0629 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/785

摘要： A CMOS device includes a substrate, a pMOS transistor and an nMOS transistor formed on the substrate, and a gated diode. The gated diode includes a floating gate formed on the substrate in between the pMOS transistor and the nMOS transistor and a pair of a p-doped region and an n-doped region formed in the substrate and between the pMOS transistor and the nMOS transistor. The n-doped region is formed between the floating gate and the nMOS transistor, and the p-doped region is formed between the floating gate and the pMOS transistor.

摘要翻译： CMOS器件包括衬底，pMOS晶体管和形成在衬底上的nMOS晶体管，以及门控二极管。 门控二极管包括形成在pMOS晶体管和nMOS晶体管之间的衬底上的浮置栅极和形成在衬底中以及在pMOS晶体管和nMOS晶体管之间的一对p掺杂区域和n掺杂区域。 在浮置栅极和nMOS晶体管之间形成n掺杂区域，并且在浮置栅极和pMOS晶体管之间形成p掺杂区域。

公开(公告)号：US20060102958A1

公开(公告)日：2006-05-18

申请号：US10990886

申请日：2004-11-16

申请人： Robert Masleid

发明人： Robert Masleid

IPC分类号： H01L29/772 ,  H01L21/335

CPC分类号： H01L21/823878 ,  H01L21/823892 ,  H01L27/0925

摘要： Systems and methods for voltage distribution via multiple epitaxial layers. In accordance with a first embodiment of the present invention, an integrated circuit comprises a wafer substrate of a connectivity type. A first epitaxial layer of a connectivity type is disposed upon a second epitaxial layer of an opposite connectivity type, which is disposed upon the wafer substrate.