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1.
公开(公告)号:US20240087628A1
公开(公告)日:2024-03-14
申请号:US18259747
申请日:2020-12-30
发明人: Guozhong XING , Huai LIN , Feng ZHANG , Di WANG , Long LIU , Changqing XIE , Ling LI , Ming LIU
CPC分类号: G11C11/161 , G11C11/1673 , G11C11/1675 , H03K19/21 , H10B61/00 , H10N50/20 , H10N50/80 , H10N50/85
摘要: A multi-resistance-state spintronic device, including: a top electrode and a bottom electrode respectively connected to a read-write circuit; and a magnetic tunnel junction between two electrodes. The magnetic tunnel junction includes from top to bottom: a ferromagnetic reference layer, a barrier tunneling layer, a ferromagnetic free layer, and a spin-orbit coupling layer. Nucleation centers are provided at two ends of the ferromagnetic free layer to generate a magnetic domain wall; the spin-orbit coupling layer is connected to the bottom electrode, and when a write pulse is applied, an electron spin current is generated and drives the magnetic domain wall through a spin-orbit torque to move; a plurality of local magnetic domain wall pinning centers are provided at an interface between the spin-orbit coupling layer and the ferromagnetic free layer to enhance a strength of a DM interaction constant between interfaces.
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公开(公告)号:US20240071451A1
公开(公告)日:2024-02-29
申请号:US18261716
申请日:2021-01-21
发明人: Huai LIN , Guozhong XING , Zuheng WU , Long LIU , Di WANG , Cheng LU , Peiwen ZHANG , Changqing XIE , Ling LI , Ming LIU
IPC分类号: G11C11/16
CPC分类号: G11C11/1673 , G11C11/1655 , G11C11/1657
摘要: The three-state spintronic device includes: a bottom electrode, a magnetic tunnel junction and a top electrode from bottom to top. The magnetic tunnel junction includes: a spin-orbit coupling layer, a ferromagnetic free layer, a barrier tunneling layer, a ferromagnetic reference layer, three local magnetic domain wall pinning centers and domain wall nucleation centers. An antisymmetric exchange interaction is modulated, and the magnetic domain wall pinning centers are embedded in an interface between a heavy metal and the ferromagnetic free layer. The magnetic domain wall nucleation centers are at two ends of the ferromagnetic free layer. A current pulse flows through the spin-orbit coupling layer to generate a spin current and the spin current is injected into the ferromagnetic free layer. Under a control of all-electrical controlled, an effective field of a spin-orbit torque drives domain wall to move and displace.
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公开(公告)号:US20210158753A1
公开(公告)日:2021-05-27
申请号:US17053992
申请日:2018-08-02
发明人: Di GENG , Yue SU , Ling LI , Nianduan LU , Ming LIU
IPC分类号: G09G3/3233 , G09G3/3291
摘要: A pixel compensation circuit including a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a first capacitor, a second capacitor, and an organic light-emitting diode, each of the first transistor to the sixth transistor including a drain, a source and a gate.
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4.
公开(公告)号:US20190006584A1
公开(公告)日:2019-01-03
申请号:US16064120
申请日:2016-08-12
发明人: Nianduan LU , Pengxiao SUN , Ling LI , Ming IIU , Qi LIU , Hangbing LV , Shibing LONG
IPC分类号: H01L45/00
摘要: A method for improving endurance of 3D integrated resistive switching memory, comprising: Step 1: Calculating the temperature distribution in the integrated array by the 3D Fourier heat conduction equation; Step 2, selecting heat transfer mode; Step 3: selecting an appropriate array structure; Step 4: analyzing the influence of integration degree on temperature in the array; Step 5: evaluating the endurance performance in the array; and Step 6: changing the array parameters according to the evaluation result to improve the endurance performance. According to the method of the present invention, based on the thermal transmission mode in the 3D integrated resistive switching device, a suitable 3D integrated array is selected to analyze the influence of the integration degree on the device temperature so as to evaluate and improve the endurance of the 3D integrated resistive switching device.
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公开(公告)号:US20230337548A1
公开(公告)日:2023-10-19
申请号:US18042249
申请日:2020-08-20
发明人: Guozhong XING , Huai LIN , Yu LIU , Peiwen ZHANG , Changqing XIE , Ling LI , Ming LIU
CPC分类号: H10N50/20 , G11C11/161 , H10B61/10 , H10N50/85 , G06F7/501 , G11C11/1673 , G11C11/1675
摘要: An SOT-driven field-free switching MRAM and an array thereof. From top to bottom, the SOT-MRAM sequentially includes: a selector (1) configured to turn on or turn off the SOT-MRAM under an action of an external voltage; a magnetic tunnel junction (2), including a ferromagnetic reference layer, a tunneling layer and a ferromagnetic free layer arranged sequentially from top to bottom; and a spin-orbit coupling layer (3) made of one or more selected from heavy metal, doped heavy metal, heavy metal alloy, metal oxide, dual heavy metal layers, semiconductor material, two-dimensional semi-metal material and anti-ferromagnetic material. The spin-orbit coupling layer is configured to generate an in-plane effective field in the ferromagnetic free layer by using the interlayer exchange coupling effect and generate spin-orbit torques by using the spin Hall effect, so as to perform a deterministic data storage in the magnetic tunnel junction (2).
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6.
公开(公告)号:US20240224820A1
公开(公告)日:2024-07-04
申请号:US18287462
申请日:2021-04-27
发明人: Guozhong XING , Huai LIN , Zuheng WU , Jiebin NIU , Zhihong YAO , Dashan SHANG , Ling LI , Ming LIU
CPC分类号: H10N70/20 , G11C13/0026 , G11C13/004 , G11C13/0069 , H10B63/30 , H10N70/841 , G11C2213/79
摘要: The present disclosure provides a memristor, including a transistor and a resistive random access memory, where a drain electrode of the transistor is connected to a bottom electrode of the resistive random access memory; and the resistive random access memory includes: the bottom electrode, a resistive random access material layer, a current compliance layer and a top electrode from bottom to top, where the current compliance layer is configured to stabilize a fluctuation of a low resistance by reducing a surge current and optimizing a heat distribution, so as to improve a calculation accuracy of a Hamming distance.
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公开(公告)号:US20230280978A1
公开(公告)日:2023-09-07
申请号:US18005756
申请日:2021-01-21
发明人: Guozhong XING , Huai LIN , Di WANG , Long LIU , Feng ZHANG , Changqing XIE , Ling LI , Ming LIU
CPC分类号: G06F7/57 , G11C11/161 , G11C11/1659 , G11C11/1673 , G11C11/1675
摘要: Provided are a spin orbit torque magnetic random access memory cell, a spin orbit torque magnetic random access memory array and a method for calculating a Hamming distance, wherein the spin orbit torque magnetic random access memory cell includes a magnetic tunnel junction; a first transistor, a drain terminal of the first transistor being connected to a bottom of the magnetic tunnel junction; and a second transistor, a drain terminal of the second transistor being connected to a top of the magnetic tunnel junction.
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公开(公告)号:US20210165027A1
公开(公告)日:2021-06-03
申请号:US16065582
申请日:2015-12-25
发明人: Guangwei XU , Zhiheng HAN , Wei WANG , Congyan LU , Lingfei WANG , Ling LI , Ming LIU
摘要: A method for obtaining a contact resistance of a planar device includes: obtaining a contact resistance of a planar device by using a potential measurement method, in the measurement of the surface potential distribution, the planar device is in a state of current flowing, a certain voltage drop is formed at a junction area of the device; extracting the voltage drop measured through the Kelvin microscope by using a linear fitting method; and dividing the measured voltage drop by the current flowing through the device, thereby accurately calculating the magnitude of the contact resistance at the junction area of the planar device. With the present invention, the contact resistance of the planar device can be precisely measured, which is suitable for the contact resistance measurement experiments of devices such as thin film transistors and diodes. The invention has the advantages of reasonable theory, accurate result, simple and easy operation, and is favorable for optimizing the device performance and establishing a complete electrical model of the device.
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