公开(公告)号：US20170356867A1

公开(公告)日：2017-12-14

申请号：US15281918

申请日：2016-09-30

申请人： Thomas Michael Daunais

发明人： Thomas Michael Daunais

IPC分类号： G01N27/04 ,  H01L21/3205 ,  H01L21/027 ,  G01N33/487 ,  G03F7/00 ,  H01L29/16 ,  H01L29/06 ,  H01L21/321

CPC分类号： G03F7/0035 ,  G01N27/4146 ,  G01N33/02 ,  G01N33/48707 ,  H01L21/32055 ,  H01L29/0669 ,  H01L29/16

摘要： A nanoscale sensor, and method to manufacture the sensor. The sensor is designed to measure the change in free carriers from analyte detection by measuring current with an applied bias across the nano-wire(s) in a tested aqueous solution. The measured current is compared to known calibrated concentrations of the tested characteristic bacterium, virus, chemical, gas, or some combination thereof and a value for the tested aqueous solution. Temperature, pH and salinity measuring circuits are included to enable environmental correction.

公开(公告)号：US20170352542A1

公开(公告)日：2017-12-07

申请号：US15522992

申请日：2015-10-29

申请人： President and Fellows of Harvard College

发明人： Charles M. Lieber ,  Ruixuan Gao ,  Max Nathan Mankin ,  Robert Day ,  Hong-Gyu Park ,  You-Shin No

IPC分类号： H01L21/02 ,  C23C16/455 ,  C23C16/56 ,  C30B25/20 ,  C30B29/06 ,  C30B29/66 ,  C30B33/10 ,  C23C16/40 ,  B82Y40/00 ,  H01L33/44 ,  H01L29/06 ,  H01L29/16 ,  H01L29/36 ,  H01L31/0216 ,  H01L31/028 ,  H01L31/0352 ,  H01L31/18 ,  H01L33/00 ,  H01L33/02 ,  H01L33/06 ,  H01L33/34

CPC分类号： H01L21/02653 ,  B82Y10/00 ,  B82Y40/00 ,  C23C16/402 ,  C23C16/45525 ,  C23C16/56 ,  C30B25/20 ,  C30B29/06 ,  C30B29/66 ,  C30B33/10 ,  H01L21/02164 ,  H01L21/0228 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02532 ,  H01L21/02584 ,  H01L21/02603 ,  H01L29/0649 ,  H01L29/068 ,  H01L29/16 ,  H01L29/365 ,  H01L29/66136 ,  H01L29/861 ,  H01L31/02161 ,  H01L31/028 ,  H01L31/035227 ,  H01L31/035272 ,  H01L31/103 ,  H01L31/1804 ,  H01L33/0054 ,  H01L33/025 ,  H01L33/06 ,  H01L33/18 ,  H01L33/34 ,  H01L33/44 ,  Y02E10/547 ,  Y02P70/521

摘要： The present invention generally relates to nanoscale wires and, in particular, to nanoscale wires with heterojunctions, such as tip-localized homo- or heterojunctions. In one aspect, the nanoscale wire may include a core, an inner shell surrounding the core, and an outer shell surrounding the inner shell. The outer shell may also contact the core, e.g., at an end portion of the nanoscale wire. In some cases, such nanoscale wires may be used as electrical devices. For example a p-n junction may be created where the inner shell is electrically insulating, and the core and the outer shell are p-doped and n-doped. Other aspects of the present invention generally relate to methods of making or using such nanoscale wires, devices, or kits including such nanoscale wires, or the like.

公开(公告)号：US09837418B2

公开(公告)日：2017-12-05

申请号：US15283085

申请日：2016-09-30

申请人： Kilopass Technology, Inc.

发明人： Harry Luan ,  Bruce L. Bateman ,  Valery Axelrad ,  Charlie Cheng

IPC分类号： H01L27/102 ,  H01L29/74 ,  H01L29/749 ,  H01L29/66 ,  H01L29/10 ,  H01L29/16 ,  H01L29/06 ,  H01L21/762 ,  H01L21/324 ,  G11C11/39 ,  H01L21/28 ,  H01L21/321 ,  H01L29/45

CPC分类号： H01L27/1027 ,  G11C11/39 ,  H01L21/28035 ,  H01L21/321 ,  H01L21/324 ,  H01L21/76224 ,  H01L28/00 ,  H01L29/0649 ,  H01L29/0834 ,  H01L29/1016 ,  H01L29/102 ,  H01L29/16 ,  H01L29/4236 ,  H01L29/45 ,  H01L29/456 ,  H01L29/66356 ,  H01L29/66363 ,  H01L29/749

摘要： A volatile memory array using vertical thyristors is disclosed together with methods of fabricating the array.

公开(公告)号：US09837317B2

公开(公告)日：2017-12-05

申请号：US15208064

申请日：2016-07-12

申请人： Unisantis Electronics Singapore Pte. Ltd.

发明人： Fujio Masuoka ,  Hiroki Nakamura

IPC分类号： H01L21/82 ,  H01L21/768 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L29/775 ,  H01L29/06 ,  B82Y10/00 ,  H01L29/423 ,  H01L29/786 ,  H01L21/265 ,  H01L21/306 ,  H01L21/324 ,  H01L29/16

CPC分类号： H01L21/823431 ,  B82Y10/00 ,  H01L21/26506 ,  H01L21/30604 ,  H01L21/30625 ,  H01L21/324 ,  H01L21/76895 ,  H01L21/823481 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/0676 ,  H01L29/16 ,  H01L29/42392 ,  H01L29/66477 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/78618 ,  H01L29/78642 ,  H01L29/78654 ,  H01L29/78696

摘要： A method for producing a semiconductor device includes forming a first fin-shaped semiconductor layer and a second fin-shaped semiconductor layer on a substrate using a sidewall formed around a dummy pattern on the substrate. A first insulating film is formed around the first fin-shaped semiconductor layer and the second fin-shaped semiconductor layer. A first pillar-shaped semiconductor layer is formed in an upper portion of the first fin-shaped semiconductor layer, and a second pillar-shaped semiconductor layer is formed in an upper portion of the second fin-shaped semiconductor layer.

公开(公告)号：US20170345923A1

公开(公告)日：2017-11-30

申请号：US15367054

申请日：2016-12-01

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Hung-Pin CHEN ,  Chi-Cherng JENG ,  Ru-Shang HSIAO ,  Li-Yi CHEN

IPC分类号： H01L29/78 ,  H01L29/423 ,  H01L29/36 ,  H01L21/265 ,  H01L29/16 ,  H01L21/306 ,  H01L29/66 ,  H01L29/417

CPC分类号： H01L29/785 ,  H01L21/26506 ,  H01L21/30604 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/16 ,  H01L29/36 ,  H01L29/41791 ,  H01L29/42356 ,  H01L29/66795 ,  H01L29/775 ,  H01L2029/7857

摘要： A semiconductor device is provided and includes a semiconductor fin protruding from a semiconductor substrate. The semiconductor fin includes plural pairs of semiconductor layers on the semiconductor substrate, each pair of semiconductor layers consists of a first semiconductor layer of a first conductivity type, and a second semiconductor layer of a second conductivity type. The second semiconductor layer is stacked on and contacts the first semiconductor layer.

公开(公告)号：US09831159B2

公开(公告)日：2017-11-28

申请号：US15132943

申请日：2016-04-19

申请人： Infineon Technologies Americas Corp.

发明人： Eung San Cho ,  Darryl Galipeau ,  Danny Clavette

IPC分类号： H01L23/64 ,  H01L23/495 ,  H01L21/48 ,  H01L23/522 ,  H01L27/06 ,  H01L29/16 ,  H02M7/00 ,  H01L23/00

CPC分类号： H01L23/49541 ,  H01L21/4853 ,  H01L23/495 ,  H01L23/49524 ,  H01L23/49537 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/5227 ,  H01L23/645 ,  H01L24/40 ,  H01L27/0617 ,  H01L29/16 ,  H01L2224/40245 ,  H01L2224/83801 ,  H01L2224/8384 ,  H01L2224/8385 ,  H01L2224/84801 ,  H01L2224/8484 ,  H01L2224/8485 ,  H01L2924/00014 ,  H01L2924/181 ,  H02M7/003 ,  H01L2924/00012 ,  H01L2224/37099

摘要： In one implementation, a semiconductor package includes a control transistor and a sync transistor of a power converter switching stage attached over a first patterned conductive carrier, as well as a magnetic material situated over leads of the first patterned conductive carrier. The semiconductor package also includes a second patterned conductive carrier attached over the first patterned conductive carrier, the control and sync transistors, and the magnetic material. Leads of the second patterned conductive carrier overlie the magnetic material and are coupled to the leads of the first patterned conductive carrier so as to form windings of an output inductor for the power converter switching stage, the output inductor being integrated into the semiconductor package.

公开(公告)号：US20170338336A1

公开(公告)日：2017-11-23

申请号：US15597469

申请日：2017-05-17

申请人： ROHM CO., LTD.

发明人： Kentaro NASU

IPC分类号： H01L29/78 ,  H01L27/02

CPC分类号： H01L29/7808 ,  H01L27/0251 ,  H01L27/0255 ,  H01L29/16 ,  H01L29/41758 ,  H01L29/4238 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/866

摘要： A semiconductor device includes a semiconductor layer that has a transistor structure including a p type source region, a p type drain region, an n type body region between the p type source region and the p type drain region, and a gate electrode facing the n type body region and a voltage-regulator diode that is disposed at the semiconductor layer and that has an n type portion connected to the p type source region and a p type portion connected to the gate electrode, in which the transistor structure and the voltage-regulator diode are unified into a single-chip configuration.

公开(公告)号：US20170338187A1

公开(公告)日：2017-11-23

申请号：US15409786

申请日：2017-01-19

申请人： TOSHIBA MEMORY CORPORATION

发明人： Takayuki KUMAI

IPC分类号： H01L23/00 ,  H01L23/58 ,  H01L23/544 ,  H01L29/04 ,  H01L29/16

CPC分类号： H01L23/562 ,  H01L23/544 ,  H01L23/585 ,  H01L29/045 ,  H01L29/16 ,  H01L2223/5446 ,  H01L2924/3512

摘要： A semiconductor device includes a substrate and a conductive layer. The substrate has an upper surface that is a substantially rectangular shape having a pair of two sides extending in a first direction and a pair of two sides extending in a second direction. The conductive layer is provided on the substrate and extending along a periphery of the substrate. The conductive layer extends and zigzags toward the first direction.

公开(公告)号：US09825151B2

公开(公告)日：2017-11-21

申请号：US15115262

申请日：2015-01-27

申请人： IUCF-HYU

发明人： Jea Gun Park ,  Tea Hun Shim ,  Seung Hyun Song ,  Du Yeong Lee

IPC分类号： H01L29/66 ,  H01L21/02 ,  H01L29/78 ,  H01L21/225 ,  H01L29/16

CPC分类号： H01L29/66795 ,  H01L21/02236 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02587 ,  H01L21/02664 ,  H01L21/2257 ,  H01L29/16 ,  H01L29/785 ,  H01L29/7854

摘要： The present invention suggests a substrate manufacturing method and a manufacturing method of a semiconductor device comprising: providing a SOI structure having an insulation layer and a silicon layer laminated on a substrate; laminating to form a silicon germanium layer and a capping silicon layer on the SOI structure; implementing oxidation process at two or more temperatures and heat treatment process at least once during the oxidation process to form a germanium cohesion layer and a silicon dioxide layer; and removing the silicon dioxide layer.

公开(公告)号：US09825044B2

公开(公告)日：2017-11-21

申请号：US15289161

申请日：2016-10-08

申请人： International Business Machines Corporation ,  GlobalFoundries, Inc.

发明人： Balasubramanian Pranatharthiharan ,  Hui Zang

IPC分类号： H01L21/76 ,  H01L27/11 ,  H01L21/02 ,  H01L29/08 ,  H01L29/66 ,  H01L21/8238

CPC分类号： H01L27/1104 ,  H01L21/0217 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/02642 ,  H01L21/3043 ,  H01L21/324 ,  H01L21/76 ,  H01L21/76224 ,  H01L21/8221 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0886 ,  H01L27/1116 ,  H01L28/00 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785

摘要： The method for preventing epitaxial growth in a semiconductor device begins with cutting a set of long fins into a set of fins of a FinFET structure, the set of fins having respective cut faces of a set of cut faces located at respective fin ends of a set of fin ends. A photoresist layer is patterned over the set of fin ends of the set of fins of the FinFET structure. The photoresist pattern over the set of fin ends differs from the photoresist pattern over other areas of the FinFET structure as the photoresist pattern over the set of fin ends protects the first dielectric material at the set of fin ends. A set of dielectric blocks is formed at the set of fin ends, wherein each of the dielectric blocks covers at least one cut face. The set of dielectric blocks prevents epitaxial growth at the set of fin ends in a subsequent epitaxial growth step.