公开(公告)号：US20180358226A1

公开(公告)日：2018-12-13

申请号：US15573772

申请日：2016-05-13

申请人： STC.UNM

发明人： Seung-Chang Lee ,  Steven R.J. Brueck

IPC分类号： H01L21/02 ,  H01L21/311 ,  H01L21/306 ,  H01L21/285 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC分类号： H01L21/02664 ,  B81C1/00111 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02236 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02532 ,  H01L21/02535 ,  H01L21/02546 ,  H01L21/02603 ,  H01L21/02639 ,  H01L21/02645 ,  H01L21/02653 ,  H01L21/2855 ,  H01L21/30608 ,  H01L21/31116 ,  H01L21/823807 ,  H01L27/092 ,  H01L27/0922 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/78681 ,  H01L29/78684 ,  H01L29/78696

摘要： Provided is a method for growing a nanowire, including: providing a substrate with a base portion having a first surface and at least one support structure extending above or below the first surface; forming a dielectric coating on the at least one support structure; forming a photoresist coating over the substrate; forming a metal coating over at least a portion of the dielectric coating; removing a portion of the dielectric coating to expose a surface of the at least one support structure; removing a portion of the at least one support structure to form a nanowire growth surface; growing at least one nanowire on the nanowire growth surface of a corresponding one of the at least one support structure, wherein the nanowire comprises a root end attached to the growth surface and an opposing, free end extending from the root end; and elastically bending the at least one nanowire.

公开(公告)号：US09893202B2

公开(公告)日：2018-02-13

申请号：US15231061

申请日：2016-08-08

申请人： Semiconductor Energy Laboratory Co., Ltd.

发明人： Junichi Koezuka ,  Masami Jintyou ,  Daisuke Kurosaki ,  Yukinori Shima ,  Toshimitsu Obonai

IPC分类号： H01L21/02 ,  H01L29/66 ,  H01L29/786

CPC分类号： H01L29/7869 ,  H01L21/0254 ,  H01L21/02554 ,  H01L21/02557 ,  H01L21/0256 ,  H01L21/02603 ,  H01L21/0262 ,  H01L21/02653 ,  H01L29/66969

摘要： A method for manufacturing a semiconductor device has a first step including a step of forming an oxide semiconductor film, a second step including a step of forming a gate insulating film over the oxide semiconductor film and a step of forming a gate electrode over the gate insulating film, a third step including a step of forming a nitride insulating film over the oxide semiconductor film and the gate electrode, a fourth step including a step of forming an oxide insulating film over the nitride insulating film, a fifth step including a step of forming an opening in the nitride insulating film and the oxide insulating film, and a sixth step including a step of forming source and drain electrodes over the oxide insulating film so as to cover the opening. In the third step, the nitride insulating film is formed through at least two steps: plasma treatment and deposition treatment. The two steps are each performed at a temperature higher than or equal to 150° C. and lower than 300° C.

公开(公告)号：US20180019122A1

公开(公告)日：2018-01-18

申请号：US15370041

申请日：2016-12-06

申请人： University of Kentucky Research Foundation

发明人： Beth S. Guiton ,  Lei Yu

IPC分类号： H01L21/02 ,  C23F1/00 ,  H01L21/465

CPC分类号： H01L21/02603 ,  C30B1/00 ,  H01L21/02381 ,  H01L21/02414 ,  H01L21/0242 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/02521 ,  H01L21/02554 ,  H01L21/02639 ,  H01L21/02645 ,  H01L21/02653 ,  H01L31/18

摘要： The present invention provides integrated nanostructures comprising a single-crystalline matrix of a material A containing aligned, single-crystalline nanowires of a material B, with well-defined crystallographic interfaces are disclosed. The nanocomposite is fabricated by utilizing metal nanodroplets in two subsequent catalytic steps: solid-liquid-vapor etching, followed by vapor-liquid-solid growth. The first etching step produces pores, or “negative nanowires” within a single-crystalline matrix, which share a unique crystallographic direction, and are therefore aligned with respect to one another. Further, since they are contained within a single, crystalline, matrix, their size and spacing can be controlled by their interacting strain fields, and the array is easily manipulated as a single entity—addressing a great challenge to the integration of freestanding nanowires into functional materials. In the second, growth, step, the same metal nanoparticles are used to fill the pores with single-crystalline nanowires, which similarly to the negative nanowires have unique growth directions, and well-defined sizes and spacings. The two parts of this composite behave synergistically, since this nanowire-filled matrix contains a dense array of well-defined crystallographic interfaces, in which both the matrix and nanowire materials convey functionality to the material. The material of either one of these components may be chosen from a vast library of any material able to form a eutectic alloy with the metal in question, including but not limited to every material thus far grown in nanowire form using the ubiquitous vapor-liquid-solid approach. This has profound implications for the fabrication of any material intended to contain a functional interface, since high interfacial areas and high quality interfacial structure should be expected. Technologies to which this simple approach could be applied include but are not limited to p-n junctions of solar cells, battery electrode arrays, multiferroic materials, and plasmonic materials.

公开(公告)号：US20180012812A1

公开(公告)日：2018-01-11

申请号：US15667305

申请日：2017-08-02

申请人： GLOBALFOUNDRIES Inc.

发明人： Suraj Kumar PATIL ,  Ajey P. JACOB

IPC分类号： H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L21/02 ,  H01L29/786 ,  H01L29/423

CPC分类号： H01L21/823885 ,  H01L21/02381 ,  H01L21/02387 ,  H01L21/02389 ,  H01L21/02392 ,  H01L21/02395 ,  H01L21/0243 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02603 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02653 ,  H01L21/823807 ,  H01L21/8258 ,  H01L27/092 ,  H01L29/0676 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/78642 ,  H01L29/78654 ,  H01L29/78681 ,  H01L29/78684 ,  H01L29/78696

摘要： A method of forming Si or Ge-based and III-V based vertically integrated nanowires on a single substrate and the resulting device are provided. Embodiments include forming first trenches in a Si, Ge, III-V, or SixGe1-x substrate; forming a conformal SiN, SiOxCyNz layer over side and bottom surfaces of the first trenches; filling the first trenches with SiOx; forming a first mask over portions of the Si, Ge, III-V, or SixGe1-x substrate; removing exposed portions of the Si, Ge, III-V, or SixGe1-x substrate, forming second trenches; forming III-V, III-VxMy, or Si nanowires in the second trenches; removing the first mask and forming a second mask over the III-V, III-VxMy, or Si nanowires and intervening first trenches; removing the SiOx layer, forming third trenches; and removing the second mask.

公开(公告)号：US20170186893A1

公开(公告)日：2017-06-29

申请号：US15457314

申请日：2017-03-13

申请人： Karin Chaudhari ,  Ashok Chaudhari ,  Pia Chaudhari

发明人： Praveen Chaudhari ,  Ashok Chaudhari

IPC分类号： H01L31/0236 ,  H01L33/22 ,  H01L33/40 ,  H01L33/24 ,  C30B29/52 ,  H01L31/18 ,  H01L33/00 ,  H01G9/20 ,  C30B23/06 ,  C30B23/02 ,  H01L31/0224 ,  H01L31/0687

CPC分类号： H01L31/02363 ,  C30B19/00 ,  C30B23/025 ,  C30B25/02 ,  C30B25/183 ,  C30B29/52 ,  H01G9/2009 ,  H01L21/0242 ,  H01L21/02422 ,  H01L21/02488 ,  H01L21/02491 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/0262 ,  H01L21/02645 ,  H01L21/02653 ,  H01L31/0687 ,  H01L31/1804 ,  H01L31/1836 ,  H01L31/1852 ,  Y02E10/544 ,  Y02E10/547 ,  Y02P70/521

摘要： A method is provided for making smooth crystalline semiconductor thin-films and hole and electron transport films for solar cells and other electronic devices. Such semiconductor films have an average roughness of 3.4 nm thus allowing for effective deposition of additional semiconductor film layers such as perovskites for tandem solar cell structures which require extremely smooth surfaces for high quality device fabrication.

公开(公告)号：US09601340B2

公开(公告)日：2017-03-21

申请号：US14474995

申请日：2014-09-02

申请人： SAMSUNG ELECTRONICS CO., LTD. ,  KOREA PHOTONICS TECHNOLOGY INSTITUTE

发明人： Jaesoong Lee ,  Hyoin Kim

IPC分类号： H01L29/16 ,  H01L27/15 ,  H01L31/12 ,  H01L33/06 ,  H01L21/285 ,  H01L29/12 ,  H01L21/02 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/06 ,  H01L29/205 ,  H01L33/18

CPC分类号： H01L21/28575 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/0254 ,  H01L21/02603 ,  H01L21/02653 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/122 ,  H01L29/205 ,  H01L33/18

摘要： Provided are electronic devices having quantum dots and methods of manufacturing the same. An electronic device includes a first nanorod, a quantum dot disposed on an upper surface of the first nanorod, and a second nanorod that covers a lateral surface of the first nanorod and the quantum dot. The first nanorod and the second nanorod are of opposite types.

公开(公告)号：US09484197B2

公开(公告)日：2016-11-01

申请号：US12910055

申请日：2010-10-22

申请人： Nathaniel Quitoriano

发明人： Nathaniel Quitoriano

IPC分类号： H01L29/04 ,  H01L21/02 ,  C30B25/02 ,  C30B29/08 ,  H01L31/18 ,  H01L27/15

CPC分类号： H01L21/02422 ,  C30B25/02 ,  C30B29/08 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/02653 ,  H01L27/153 ,  H01L31/1804 ,  Y02E10/547 ,  Y02P70/521

摘要： A method of growing high quality crystalline films on lattice-mismatched or amorphous layers is presented allowing semiconductor materials that would normally be subject to high stress and cracking to be employed allowing cost reductions and/or performance improvements in devices to be obtained. Catalysis of the growth of these films is based upon utilizing particular combinations of metals, materials, and structures to establish growth of the crystalline film from a predetermined location. The subsequent film growth occurring in one or two dimensions to cover a predetermined area of the amorphous or lattice-mismatched substrate. Accordingly the technique can be used to either cover a large area or provide tiles of crystalline material with or without crystalline film interconnections.

摘要翻译： 提出了在晶格失配或非晶层上生长高质量结晶膜的方法，允许通常采用高应力和开裂的半导体材料，从而可以获得要获得的器件的成本降低和/或性能改进。 这些膜的生长的催化基于利用金属，材料和结构的特定组合来建立晶体膜从预定位置的生长。 随后的膜生长以一维或二维发生，以覆盖非晶形或晶格失配衬底的预定区域。 因此，该技术可以用于覆盖大面积或提供具有或不具有结晶膜互连的结晶材料的瓦片。

公开(公告)号：US20160178605A1

公开(公告)日：2016-06-23

申请号：US15058846

申请日：2016-03-02

申请人： Mohammad Abdolahad ,  Milad Gharooni ,  Shamsoddin Mohajerzadeh ,  Hamed Abiri ,  Mohsen Janmaleki

发明人： Mohammad Abdolahad ,  Milad Gharooni ,  Shamsoddin Mohajerzadeh ,  Hamed Abiri ,  Mohsen Janmaleki

IPC分类号： G01N33/483 ,  H01L21/02 ,  G01N27/22

CPC分类号： G01N33/4836 ,  G01N27/02 ,  G01N27/021 ,  G01N27/3278 ,  G01N33/5011 ,  G01N33/5044 ,  G01N33/574 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/02645 ,  H01L21/02653

摘要： An electrical cell-substrate impedance sensor (ECIS) includes a substrate; a catalyst layer formed on the substrate; and a plurality of nanowire electrodes array grown on the catalyst layer. The plurality of nanowire electrodes are configured to measure an electrical response of a biological cell.

摘要翻译： 电池基片阻抗传感器（ECIS）包括基片; 形成在所述基板上的催化剂层; 以及在催化剂层上生长的多个纳米线电极阵列。 多个纳米线电极被配置为测量生物细胞的电响应。

公开(公告)号：US09231053B2

公开(公告)日：2016-01-05

申请号：US14314177

申请日：2014-06-25

申请人： HONEYWELL INTERNATIONAL INC.

发明人： Raju Addepalle Raghurama ,  Basavaraja Sangappa Devaramani

IPC分类号： H01L29/06 ,  H01L29/20 ,  H01L29/22 ,  H01L33/28 ,  H01L33/30 ,  H01L33/12 ,  H01L21/02 ,  H01L29/267

CPC分类号： H01L29/0676 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02472 ,  H01L21/02513 ,  H01L21/02554 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/02603 ,  H01L21/0262 ,  H01L21/02645 ,  H01L21/02653 ,  H01L21/02658 ,  H01L29/0673 ,  H01L29/2003 ,  H01L29/22 ,  H01L29/267 ,  H01L33/12

摘要： Semiconductor devices useful as light emitting diodes or power transistors are provided. The devices produced by depositing a Zn—O-based layer comprising nanostructures on a Si-based substrate, with or without a metal catalyst layer deposited therebetween. Furthermore, a pair of adjacent p-n junction forming layers is deposited on the ZnO-based layer, where one of the pair is an n-type epitaxial layer, and the other is a p-type epitaxial layer. One or more epitaxial layers may, optionally, be deposited between the ZnO-based layer and the pair of adjacent p-n junction forming layers.

摘要翻译： 提供用作发光二极管或功率晶体管的半导体器件。 通过在Si基衬底上沉积包含纳米结构的Zn-O基层，其中沉积有或没有沉积金属催化剂层而制备的器件。 此外，一对相邻的p-n结形成层沉积在ZnO基层上，其中一对是n型外延层，另一个是p型外延层。 可以任选地在ZnO基层和一对相邻的p-n结形成层之间沉积一个或多个外延层。

公开(公告)号：US20150368831A1

公开(公告)日：2015-12-24

申请号：US14742932

申请日：2015-06-18

申请人： King Abdullah University of Science and Technology

发明人： Tao Wu ,  Guodong Li

IPC分类号： C30B25/14 ,  C30B29/60 ,  C30B25/10 ,  C30B25/12

CPC分类号： C30B29/60 ,  B82Y40/00 ,  C30B23/00 ,  C30B25/00 ,  C30B29/16 ,  C30B29/48 ,  H01L21/02554 ,  H01L21/02603 ,  H01L21/02645 ,  H01L21/02653

摘要： Various methods and systems are provided for production of nanowires or other nanomaterials. In one example, among others, a system includes a furnace configured to heat at least a portion of a tube, a material feeder coupled to a first end of the tube, and a vacuum pumping system coupled to a second end of the tube. The material feeder can include a source material manipulator that can position a source material in a fixture of a feeder arm and a linear manipulator that can extend the fixture into the tube, where it can be heated to produce a precursor vapor that can be used to form a nanomaterial on a substrate. In another example, a method includes extending a fixture holding source material into a furnace tube, drawing a precursor vapor produced from the source material across a substrate in the furnace tube, and forming nanomaterial on the substrate.

摘要翻译： 为纳米线或其他纳米材料的生产提供了各种方法和系统。 在一个示例中，系统包括构造成加热管的至少一部分的炉，连接到管的第一端的材料供给器和耦合到管的第二端的真空泵送系统。 材料馈送器可以包括源材料操纵器，其可以将源材料定位在馈送臂的固定装置中，以及线性操纵器，其可以将固定装置延伸到管中，在那里可以将其加热以产生可用于 在衬底上形成纳米材料。 在另一个实例中，一种方法包括将夹持源材料延伸到炉管中，从源材料产生的前体蒸汽穿过炉管中的衬底，并在衬底上形成纳米材料。