公开(公告)号：US11946157B2

公开(公告)日：2024-04-02

申请号：US17743039

申请日：2022-05-12

申请人： ASM IP Holding B.V.

发明人： Rami Khazaka ,  Qi Xie

IPC分类号： C30B25/10 ,  C30B29/06 ,  C30B29/08 ,  C30B33/12

CPC分类号： C30B25/10 ,  C30B29/06 ,  C30B29/08 ,  C30B33/12

摘要： Methods and devices for epitaxially growing boron doped silicon germanium layers. The layers may be used, for example, as a p-type source and/or drain regions in field effect transistors.

公开(公告)号：US20240011193A1

公开(公告)日：2024-01-11

申请号：US18041554

申请日：2021-08-19

申请人： SOCPRA SCIENCES ET GENIE S.E.C.

发明人： Youcef Ataellah BIOUD ,  Abderraouf BOUCHERIF ,  Richard ARÈS

IPC分类号： C30B33/10 ,  H01L21/02 ,  C30B29/08 ,  C30B33/02 ,  C30B31/22 ,  C25F3/12

CPC分类号： C30B33/10 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02513 ,  C30B29/08 ,  C30B33/02 ,  C30B31/22 ,  C25F3/12

摘要： There is described a method of manufacturing a substrate for an optoelectronic device. The method has the steps of: supporting a first layer of a first crystalline material on a second layer of a second crystalline material different from said first crystalline material thereby exposing crystalline defects at a surface of said first layer; etching said first layer using first etching conditions, at least some of said crystalline defects expanding into pores running from said surface of the first layer towards said second layer; and heating said first and second layers up to a first temperature for a first period of time within a given environment, said heating transforming said pores into nanovoids attracting at least some of said crystalline defects away from said surface. In some embodiments, the method has a step of reheating the layers or a step of forming a pore containing region within the first layer.

公开(公告)号：US20180175371A1

公开(公告)日：2018-06-21

申请号：US15579029

申请日：2016-06-01

申请人： University of Limerick

发明人： Kevin M. Ryan ,  Tadhg Kennedy

IPC分类号： H01M4/134 ,  H01M4/36 ,  H01M4/38 ,  H01M10/0525 ,  C30B29/06 ,  C30B29/08 ,  C30B29/66 ,  C30B11/12 ,  C30B25/18

CPC分类号： H01M4/134 ,  C30B11/12 ,  C30B25/18 ,  C30B29/06 ,  C30B29/08 ,  C30B29/52 ,  C30B29/60 ,  C30B29/66 ,  H01M4/366 ,  H01M4/38 ,  H01M4/386 ,  H01M10/0525

摘要： The present invention provides a heterostructure for use as an electrode in a lithium ion battery as well as a method for synthesising the heterostructure.

公开(公告)号：US09865467B2

公开(公告)日：2018-01-09

申请号：US14919381

申请日：2015-10-21

申请人： TOKYO ELECTRON LIMITED

发明人： Daisuke Suzuki ,  Youichirou Chiba ,  Takumi Yamada

IPC分类号： H01L21/285 ,  H01L21/02 ,  H01L21/306 ,  H01L21/324 ,  H01L21/768 ,  C30B1/02 ,  C30B29/06 ,  C30B29/08 ,  H01L21/74 ,  C23C16/04

CPC分类号： H01L21/28525 ,  C23C16/045 ,  C30B1/023 ,  C30B29/06 ,  C30B29/08 ,  H01L21/0243 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/28556 ,  H01L21/324 ,  H01L21/743 ,  H01L21/76843 ,  H01L21/76876 ,  H01L21/76879

摘要： There is provided a method of filling a recess of a workpiece, which includes: forming a first thin film made of a semiconductor material along a wall surface defining a recess in a semiconductor substrate; annealing the workpiece within a vessel whose internal process is set to a first pressure, and forming an epitaxial region which is generated by crystallizing the semiconductor material of the first thin film, along a surface defining the recess, without moving the first thin film; forming a second thin film made of the semiconductor material along the wall surface defining the recess; and annealing the workpiece within the vessel whose internal pressure is set to a second pressure lower than the first pressure, and forming a further epitaxial region which is generated by crystallizing the semiconductor material of the second thin film which is moved toward a bottom of the recess.

公开(公告)号：US20170178903A1

公开(公告)日：2017-06-22

申请号：US15386592

申请日：2016-12-21

申请人： U.S.A. as represented by the Administrator of the National Aeronautics and Space Administration

发明人： Sang Hyouk Choi ,  Adam J. Duzik

IPC分类号： H01L21/02 ,  C30B29/20 ,  C30B23/06 ,  C30B29/52 ,  H01L29/161 ,  C30B23/08

CPC分类号： H01L21/02532 ,  C30B23/063 ,  C30B23/08 ,  C30B29/06 ,  C30B29/08 ,  C30B29/20 ,  C30B29/52 ,  H01L21/0242 ,  H01L21/02433 ,  H01L21/02598 ,  H01L21/02609 ,  H01L21/02617 ,  H01L29/161

摘要： Various embodiments may provide a low temperature (i.e., less than 850° C.) method of Silicon-Germanium (SiGe) on sapphire (Al2O3) (SiGe/sapphire) growth that may produce a single crystal film with less thermal loading effort to the substrate than conventional high temperature (i.e., temperatures above 850° C.) methods. The various embodiments may alleviate the thermal loading requirement of the substrate, which in conventional high temperature (i.e., temperatures above 850° C.) methods had surface temperatures within the range of 850° C.-900° C. The various embodiments may provide a new thermal loading requirement of the sapphire substrate for growing single crystal SiGe on the sapphire substrate in the range of about 450° C. to about 500° C.

公开(公告)号：US09528196B2

公开(公告)日：2016-12-27

申请号：US14131295

申请日：2012-07-25

申请人： Michel Bruel

发明人： Michel Bruel

IPC分类号： C30B11/14 ,  C30B19/10 ,  H01L21/02 ,  C30B19/00 ,  C30B29/06 ,  C30B29/08 ,  C30B19/06

CPC分类号： C30B19/10 ,  C30B19/00 ,  C30B19/062 ,  C30B29/06 ,  C30B29/08 ,  H01L21/02532 ,  H01L21/02625

摘要： The invention concerns a method for fabricating a substrate in semiconductor material characterized in that it comprises the steps of: starting from a donor substrate in a first semiconductor material at an initial temperature, contacting a surface of the donor substrate with a bath of a second semiconductor material held in the liquid state at a temperature higher than the initial temperature, the second semiconductor material being chosen so that its melting point is equal to or lower than the melting point of the first semiconductor material, solidifying the bath material on the surface to thicken the donor substrate with a solidified layer. The invention also concerns a device for implementing the method.

摘要翻译： 本发明涉及一种用于制造半导体材料中的衬底的方法，其特征在于其包括以下步骤：从初始温度下的第一半导体材料中的施主衬底开始，将供体衬底的表面与第二半导体 在高于初始温度的温度下保持在液态的材料，选择第二半导体材料使其熔点等于或低于第一半导体材料的熔点，使表面上的浴材固化成稠化 施主衬底具有固化层。 本发明还涉及一种用于实现该方法的装置。

公开(公告)号：US20160369393A1

公开(公告)日：2016-12-22

申请号：US15256855

申请日：2016-09-06

申请人： Wacker Chemie AG

发明人： Laszlo FABRY ,  Mikhail SOFIN

IPC分类号： C23C16/22 ,  C23C16/02

CPC分类号： C23C16/22 ,  C01B33/035 ,  C22C28/00 ,  C23C16/0209 ,  C30B13/00 ,  C30B15/02 ,  C30B29/06 ,  C30B29/08 ,  C30B29/52 ,  Y10T428/298

摘要： A rod having a length of 0.5 m to 4 m and having a diameter of 25 mm to 220 mm, comprising a high-purity alloy composed of 0.1 to 50 mol % germanium and 99.9 to 50 mol % silicon, the alloy having been deposited on a thin silicon rod or on a thin germanium-alloyed silicon rod, the deposited alloy having a polycrystalline structure.

摘要翻译： 长度为0.5μm至4μm，直径为25mm至220mm的棒，包括由0.1至50mol％的锗和99.9至50mol％的硅组成的高纯度合金，该合金已沉积在 薄硅棒或薄的锗合金硅棒，沉积合金具有多晶结构。

公开(公告)号：US20160237591A1

公开(公告)日：2016-08-18

申请号：US15027566

申请日：2014-10-13

申请人： CORNELL UNIVERSITY

发明人： Tobias HANRATH ,  Benjamin T. RICHARDS

IPC分类号： C30B23/06 ,  C23C18/12 ,  B22F1/00 ,  B22F1/02 ,  C25D3/38 ,  C25D7/06 ,  C30B7/12 ,  C30B7/14 ,  C30B25/10 ,  C30B30/02 ,  C30B29/62 ,  C30B29/06 ,  C30B29/08 ,  C30B29/52 ,  C30B29/02 ,  C23C14/16

CPC分类号： C30B23/063 ,  B22F1/0025 ,  B22F1/025 ,  C23C14/16 ,  C23C14/562 ,  C23C18/06 ,  C23C18/08 ,  C23C18/1204 ,  C23C18/1241 ,  C23C18/1262 ,  C23C18/1291 ,  C25D3/38 ,  C25D7/0614 ,  C30B7/12 ,  C30B7/14 ,  C30B25/10 ,  C30B29/02 ,  C30B29/06 ,  C30B29/08 ,  C30B29/52 ,  C30B29/60 ,  C30B29/62 ,  C30B30/02 ,  C30B33/00

摘要： Growth of Group IV nanowires with a substrate and a Group IV metalloid is performed using resistive or inductive heating of the substrate. A roll-to-roll process enables a metal surface to move through a reaction environment while reacting with a stream or bath of precursor to form the nanowire-metal complex. The Group IV nanowires on a surface of the substrate can have a surface loading greater than 10 mg/cm2.

摘要翻译： 使用基板和基板的电阻或感应加热来进行具有基板和IV族准金属的IV族纳米线的生长。 卷对卷过程使得金属表面能够通过反应环境移动，同时与前体的流或浴反应形成纳米线 - 金属络合物。 衬底表面上的IV族纳米线可以具有大于10mg / cm 2的表面负载。

公开(公告)号：US09382642B2

公开(公告)日：2016-07-05

申请号：US13259818

申请日：2010-04-16

申请人： Srinivas Yarlagadda ,  Natale Speciale ,  Franco Preti ,  Mario Preti

发明人： Srinivas Yarlagadda ,  Natale Speciale ,  Franco Preti ,  Mario Preti

IPC分类号： C30B35/00 ,  C30B25/08 ,  C23C16/46 ,  C30B25/10 ,  C30B29/06 ,  C30B29/08 ,  C30B29/36 ,  C30B29/40

CPC分类号： C30B25/08 ,  C23C16/46 ,  C30B25/10 ,  C30B29/06 ,  C30B29/08 ,  C30B29/36 ,  C30B29/403 ,  C30B29/406 ,  C30B35/00

摘要： The present invention relates to a reaction chamber of an epitaxial reactor that essentially consists of a quartz piece; the quartz piece comprises a quartz piece portion (1) having an internal cavity (2) defined by walls (1A, 1B, 1C, 1D); the cavity (2) comprises a reaction and deposition zone (3) of the epitaxial reactor; the zone (3) is adapted to house a susceptor (4) to be heated therein; the reaction chamber also comprises a quartz component (5) arranged close to said walls (1A, 1B, 1C, 1D) in such a manner as to form a counterwall and to be a wall of said zone (3).

摘要翻译： 本发明涉及一种基本上由石英片组成的外延反应器的反应室; 石英片包括具有由壁（1A，1B，1C，1D）限定的内腔（2）的石英片部分（1）; 空腔（2）包括外延反应器的反应和沉积区（3）; 所述区域（3）适于容纳待加热的基座（4）; 反应室还包括以形成对置壁并且成为所述区域（3）的壁的方式布置在所述壁（1A，1B，1C，1D）附近的石英组件（5）。

公开(公告)号：US20160126095A1

公开(公告)日：2016-05-05

申请号：US14933554

申请日：2015-11-05

申请人： COMMISSARIAT À L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

发明人： Yann BOGUMILOWICZ ,  Jean-Michel HARTMANN

IPC分类号： H01L21/02 ,  C30B25/16 ,  C30B29/68 ,  C30B29/08 ,  C30B29/40 ,  C30B29/42 ,  C30B25/18 ,  C30B29/06

CPC分类号： H01L21/02636 ,  C30B25/16 ,  C30B25/183 ,  C30B29/06 ,  C30B29/08 ,  C30B29/40 ,  C30B29/42 ,  C30B29/68 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/0245 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02505 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/0262

摘要： First, second and third series of samples are successively made so as to determine the influence of the deposition parameters on the crystallographic quality of a layer of semiconductor material of III-V type. The parameters studied are successively the deposition pressure, the deposition temperature and the deposited thickness of a sub-layer of semiconductor material of III-V type so as to respectively determine a first deposition pressure, a first deposition temperature at the first deposition pressure, and a first deposited thickness at the first deposition temperature and at the first deposition pressure. The sub-layer of semiconductor material of III-V type is thickened by ways of a second layer of semiconductor material of III-V type deposited under different conditions.

摘要翻译： 首先，第二和第三系列样品依次进行，以确定沉积参数对III-V型半导体材料层的晶体学质量的影响。 所研究的参数依次是III-V型半导体材料的子层的沉积压力，沉积温度和沉积厚度，以分别确定第一沉积压力，第一沉积压力下的第一沉积温度，以及 在第一沉积温度和第一沉积压力下的第一沉积厚度。 III-V型半导体材料的子层通过在不同条件下沉积的III-V型第二半导体材料层的方式来增厚。