公开(公告)号：US20110101533A1

公开(公告)日：2011-05-05

申请号：US12611285

申请日：2009-11-03

Applicant: Sang Won Yoon ,  Alexandros Margomenos

Inventor： Sang Won Yoon ,  Alexandros Margomenos

IPC: H01L23/498 ,  H01L21/98

CPC classification number: H01L25/0657 ,  B81C1/00238 ,  B81C2203/0771 ,  B81C2203/0792 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/11003 ,  H01L2224/111 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/1148 ,  H01L2224/1184 ,  H01L2224/11845 ,  H01L2224/11849 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1329 ,  H01L2224/13299 ,  H01L2224/133 ,  H01L2224/276 ,  H01L2224/2784 ,  H01L2224/27845 ,  H01L2224/29011 ,  H01L2224/29101 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/30181 ,  H01L2224/73104 ,  H01L2224/811 ,  H01L2224/81903 ,  H01L2224/83101 ,  H01L2224/83203 ,  H01L2224/838 ,  H01L2224/8385 ,  H01L2224/9221 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06562 ,  H01L2225/06565 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07811 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/1579 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/01027 ,  H01L2924/3512

Abstract: A process of forming a semiconductor integrated circuit that includes the steps of: forming at least a first element having a first pattern of conductive material and including a polymer layer surrounding the conductive material, forming at least a second element having a second pattern of conductive material and including a polymer layer surrounding the conductive material, positioning the first element relative to the second element, and bonding the polymer layer of the first and second elements at a temperature below a melting temperature of the conductive materials of the first and second elements wherein the conductive material of the first element contacts the conductive material of the second element and is maintained in position by the bonded polymer layers.

Abstract translation: 一种形成半导体集成电路的方法，包括以下步骤：至少形成具有导电材料的第一图案的第一元件，并且包括围绕导电材料的聚合物层，至少形成具有第二导电材料图案的第二元件 并且包括围绕所述导电材料的聚合物层，相对于所述第二元件定位所述第一元件，以及在低于所述第一和第二元件的导电材料的熔融温度的温度下将所述第一和第二元件的聚合物层粘合，其中 第一元件的导电材料接触第二元件的导电材料，并通过结合的聚合物层保持在适当的位置。

公开(公告)号：US09245834B2

公开(公告)日：2016-01-26

申请号：US13422981

申请日：2012-03-16

Applicant: Ming-Che Hsieh

Inventor： Ming-Che Hsieh

IPC: H01L23/48 ,  H01L23/498 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L23/49816 ,  H01L21/4853 ,  H01L21/561 ,  H01L21/563 ,  H01L23/49811 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/03472 ,  H01L2224/03474 ,  H01L2224/0348 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05686 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11903 ,  H01L2224/13011 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/13076 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/13186 ,  H01L2224/1319 ,  H01L2224/1329 ,  H01L2224/13299 ,  H01L2224/16112 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/48091 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81191 ,  H01L2224/814 ,  H01L2224/81411 ,  H01L2224/81815 ,  H01L2224/83104 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/00013 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/01074 ,  H01L2924/04941 ,  H01L2924/0665 ,  H01L2924/05442 ,  H01L2924/05042 ,  H01L2924/05432 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/05599

Abstract: A semiconductor device has a semiconductor die. The semiconductor die has a contact pad. A first conductive layer is formed over the contact pad. A conductive shell having a hollow core is formed over the first conductive layer. A compliant material is deposited in the hollow core. The semiconductor die is mounted over a substrate with the conductive shell electrically connected to a conductive trace on the substrate. A second conductive layer is formed over the conductive shell. The compliant material is an insulating material. A bump material is deposited around the conductive shell. A pre-solder material is deposited over the conductive trace. The conductive shell has a cross-sectional width less than 7 micrometers. The second conductive layer is a conductive lip. Mounting the semiconductor die over the substrate further includes mounting the semiconductor die over the substrate in a bump on lead (BOL) configuration.

Abstract translation: 半导体器件具有半导体管芯。 半导体管芯具有接触焊盘。 在接触垫上形成第一导电层。 具有中空芯的导电壳形成在第一导电层的上方。 柔性材料沉积在中空芯中。 半导体管芯安装在衬底上，导电壳电连接到衬底上的导电迹线。 在导电外壳上形成第二导电层。 柔顺材料是绝缘材料。 凸起材料沉积在导电外壳周围。 预焊材料沉积在导电迹线上。 导电壳的横截面宽度小于7微米。 第二导电层是导电唇缘。 将半导体管芯安装在衬底上还包括将半导体管芯安装在衬底上的引线（BOL）构造上的凸块中。

公开(公告)号：US20160284639A1

公开(公告)日：2016-09-29

申请号：US14856469

申请日：2015-09-16

Applicant: CHIPMOS TECHNOLOGIES INC ,  CHIPMOS TECHNOLOGIES (BERMUDA) LTD.

Inventor： SHENG-PAI CHEN

IPC: H01L23/528 ,  H01L23/00

CPC classification number: H01L23/528 ,  H01L23/3114 ,  H01L23/3192 ,  H01L23/525 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L23/562 ,  H01L24/02 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02311 ,  H01L2224/02331 ,  H01L2224/0235 ,  H01L2224/02351 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05551 ,  H01L2224/05557 ,  H01L2224/1134 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11849 ,  H01L2224/1191 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/132 ,  H01L2224/13299 ,  H01L2924/351 ,  H01L2924/3512 ,  H01L2924/35121 ,  H01L2924/00012 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/01028 ,  H01L2924/014 ,  H01L2924/00014

Abstract: The present disclosure relates to a semiconductor structure, which includes a semiconductor substrate, an insulating layer and a plurality of wirings. The insulating layer is disposed on the semiconductor substrate. The plurality of wirings are disposed between the semiconductor substrate and the insulating layer. At least one wiring of the wirings includes a plurality of holes, and a total area of the holes is from 10% to 70% of a surface area of the at least one wiring.

Abstract translation: 本公开涉及一种半导体结构，其包括半导体衬底，绝缘层和多个布线。 绝缘层设置在半导体衬底上。 多个布线设置在半导体衬底和绝缘层之间。 布线的至少一个布线包括多个孔，并且孔的总面积为至少一个布线的表面积的10％至70％。

公开(公告)号：US20130241071A1

公开(公告)日：2013-09-19

申请号：US13422981

申请日：2012-03-16

Applicant: Ming-Che Hsieh

Inventor： Ming-Che Hsieh

IPC: H01L23/498 ,  H01L21/60

CPC classification number: H01L23/49816 ,  H01L21/4853 ,  H01L21/561 ,  H01L21/563 ,  H01L23/49811 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/03472 ,  H01L2224/03474 ,  H01L2224/0348 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05686 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11903 ,  H01L2224/13011 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/13076 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/13186 ,  H01L2224/1319 ,  H01L2224/1329 ,  H01L2224/13299 ,  H01L2224/16112 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/48091 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81191 ,  H01L2224/814 ,  H01L2224/81411 ,  H01L2224/81815 ,  H01L2224/83104 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/00013 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/01074 ,  H01L2924/04941 ,  H01L2924/0665 ,  H01L2924/05442 ,  H01L2924/05042 ,  H01L2924/05432 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/05599

Abstract: A semiconductor device has a semiconductor die. The semiconductor die has a contact pad. A first conductive layer is formed over the contact pad. A conductive shell having a hollow core is formed over the first conductive layer. A compliant material is deposited in the hollow core. The semiconductor die is mounted over a substrate with the conductive shell electrically connected to a conductive trace on the substrate. A second conductive layer is formed over the conductive shell. The compliant material is an insulating material. A bump material is deposited around the conductive shell. A pre-solder material is deposited over the conductive trace. The conductive shell has a cross-sectional width less than 7 micrometers. The second conductive layer is a conductive lip. Mounting the semiconductor die over the substrate further includes mounting the semiconductor die over the substrate in a bump on lead (BOL) configuration.

Abstract translation: 半导体器件具有半导体管芯。 半导体管芯具有接触焊盘。 在接触垫上形成第一导电层。 具有中空芯的导电壳形成在第一导电层的上方。 柔性材料沉积在中空芯中。 半导体管芯安装在衬底上，导电壳电连接到衬底上的导电迹线。 在导电外壳上形成第二导电层。 柔顺材料是绝缘材料。 凸起材料沉积在导电外壳周围。 预焊材料沉积在导电迹线上。 导电壳的横截面宽度小于7微米。 第二导电层是导电唇缘。 将半导体管芯安装在衬底上还包括将半导体管芯安装在衬底上的引线（BOL）构造上的凸块中。

公开(公告)号：US20120104574A1

公开(公告)日：2012-05-03

申请号：US12914274

申请日：2010-10-28

Applicant: Josef Boeck ,  Rudolf Lachner ,  Maciej Wojnowski ,  Thorsten Meyer

Inventor： Josef Boeck ,  Rudolf Lachner ,  Maciej Wojnowski ,  Thorsten Meyer

IPC: H01L23/552 ,  H01L21/50 ,  H01L23/52

CPC classification number: H01L24/20 ,  G01S7/032 ,  H01L23/49816 ,  H01L23/66 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/19 ,  H01L24/32 ,  H01L24/81 ,  H01L24/96 ,  H01L2223/6677 ,  H01L2224/0401 ,  H01L2224/11318 ,  H01L2224/1132 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/1319 ,  H01L2224/13191 ,  H01L2224/13299 ,  H01L2224/14051 ,  H01L2224/141 ,  H01L2224/14505 ,  H01L2224/14517 ,  H01L2224/16225 ,  H01L2224/17517 ,  H01L2224/21 ,  H01L2224/2101 ,  H01L2224/211 ,  H01L2224/215 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81801 ,  H01L2224/831 ,  H01L2924/01029 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/3512 ,  H01L2924/384 ,  H01Q1/44 ,  H01Q17/00 ,  H01Q23/00 ,  H05K3/3436 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A semiconductor module having one or more integrated antennas in a single package is provided herein to comprise a bonding interconnect structure having a plurality of individual bonding elements that are confined to a relatively small area of the bottom of a package. In particular, the semiconductor module comprises a bonding interconnect structure configured to connect an integrated package to a printed circuit board (PCB), wherein the integrated antenna structures are located at greater center-to-center distance from the IC device than the three dimensional interconnect structures. Therefore, the bonding interconnect structures are confined to a connection area that causes a part of the package containing the one or more antenna structures to extend beyond the bonding interconnect structure as a cantilevered structure. Such a bonding interconnect structure result in a package that is in contact with a PCB at a relatively small area that supports the load of the package.

Abstract translation: 本文提供了在单个封装中具有一个或多个集成天线的半导体模块，其包括具有限定在封装的底部的较小区域的多个单独的结合元件的接合互连结构。 特别地，半导体模块包括被配置为将集成封装连接到印刷电路板（PCB）的接合互连结构，其中集成天线结构位于距离IC器件更大的中心到距离三维互连 结构。 因此，接合互连结构被限制在连接区域上，该连接区域使得包含一个或多个天线结构的封装的一部分延伸超过作为悬臂结构的接合互连结构。 这种接合互连结构导致在支撑封装负载的较小区域处与PCB接触的封装。

公开(公告)号：US20060211461A1

公开(公告)日：2006-09-21

申请号：US11403492

申请日：2006-04-13

Applicant: James Hattis

Inventor： James Hattis

IPC: B41L1/24

CPC classification number: H01L24/17 ,  H01L23/3677 ,  H01L24/13 ,  H01L24/14 ,  H01L24/81 ,  H01L2224/10135 ,  H01L2224/10165 ,  H01L2224/131 ,  H01L2224/13291 ,  H01L2224/13299 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/14135 ,  H01L2224/14505 ,  H01L2224/16 ,  H01L2224/17519 ,  H01L2224/81141 ,  H01L2224/81385 ,  H01L2224/81902 ,  H01L2224/94 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01041 ,  H01L2924/01057 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H05K1/0204 ,  H05K3/0061 ,  H05K2201/0154 ,  H05K2201/10674 ,  H01L2224/11 ,  H01L2224/0401

Abstract: A method and apparatus for improving the thermal conductivity of a circuit board (CB) assembly comprising an integrated circuit (IC) die mounted on a CB. A high thermal conductivity device is attached on a first end to a surface of the die. When the die is mounted on the CB, a void formed in the CB receives a second end of the HTC device, and the second end of the HTC device comes into contact with a portion of the CB. During operation of the die, heat produced by the die is dissipated through the HTC device and into the CB.

Abstract translation: 一种用于改善电路板（CB）组件的热导率的方法和装置，其包括安装在CB上的集成电路（IC）模具。 高导热性装置在第一端附接到模具的表面。 当芯片安装在CB上时，形成在CB中的空隙接收HTC设备的第二端，并且HTC设备的第二端与CB的一部分接触。 在模具的操作期间，由模具产生的热量通过HTC装置消散并进入CB。

公开(公告)号：US09064787B2

公开(公告)日：2015-06-23

申请号：US13868191

申请日：2013-04-23

Applicant: Infineon Technologies AG

Inventor： Josef Boeck ,  Rudolf Lachner ,  Maciej Wojnowski ,  Thorsten Meyer

IPC: H05K1/18 ,  H01L23/00 ,  H01L23/498 ,  H01L23/66 ,  H01Q1/44 ,  H01Q17/00 ,  H01Q23/00 ,  G01S7/03 ,  H05K3/34

CPC classification number: H01L24/20 ,  G01S7/032 ,  H01L23/49816 ,  H01L23/66 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/19 ,  H01L24/32 ,  H01L24/81 ,  H01L24/96 ,  H01L2223/6677 ,  H01L2224/0401 ,  H01L2224/11318 ,  H01L2224/1132 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/1319 ,  H01L2224/13191 ,  H01L2224/13299 ,  H01L2224/14051 ,  H01L2224/141 ,  H01L2224/14505 ,  H01L2224/14517 ,  H01L2224/16225 ,  H01L2224/17517 ,  H01L2224/21 ,  H01L2224/2101 ,  H01L2224/211 ,  H01L2224/215 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81801 ,  H01L2224/831 ,  H01L2924/01029 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/3512 ,  H01L2924/384 ,  H01Q1/44 ,  H01Q17/00 ,  H01Q23/00 ,  H05K3/3436 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A semiconductor module having one or more integrated antennas in a single package is provided herein. The semiconductor module has a bonding interconnect structure that connects an integrated package to a printed circuit board (PCB), wherein the integrated antenna structures are located at greater center-to-center distance from the IC device than the three dimensional interconnect structures. Therefore, the bonding interconnect structures are confined to a connection area that causes a part of the package containing the one or more antenna structures to extend beyond the bonding interconnect structure as a cantilevered structure. Such a bonding interconnect structure result in a package that is in contact with a PCB at a relatively small area that supports the load of the package.

Abstract translation: 本文提供了在单个封装中具有一个或多个集成天线的半导体模块。 半导体模块具有将集成封装连接到印刷电路板（PCB）的接合互连结构，其中集成天线结构位于距离IC器件比三维互连结构更大的中心到中心距离处。 因此，接合互连结构被限制在连接区域上，该连接区域使得包含一个或多个天线结构的封装的一部分延伸超过作为悬臂结构的接合互连结构。 这种接合互连结构导致在支撑封装负载的较小区域处与PCB接触的封装。

公开(公告)号：US20130241059A1

公开(公告)日：2013-09-19

申请号：US13868191

申请日：2013-04-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Josef Boeck ,  Rudolf Lachner ,  Maciej Wojnowski ,  Thorsten Meyer

IPC: H01L23/00

CPC classification number: H01L24/20 ,  G01S7/032 ,  H01L23/49816 ,  H01L23/66 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/19 ,  H01L24/32 ,  H01L24/81 ,  H01L24/96 ,  H01L2223/6677 ,  H01L2224/0401 ,  H01L2224/11318 ,  H01L2224/1132 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/1319 ,  H01L2224/13191 ,  H01L2224/13299 ,  H01L2224/14051 ,  H01L2224/141 ,  H01L2224/14505 ,  H01L2224/14517 ,  H01L2224/16225 ,  H01L2224/17517 ,  H01L2224/21 ,  H01L2224/2101 ,  H01L2224/211 ,  H01L2224/215 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81801 ,  H01L2224/831 ,  H01L2924/01029 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/3512 ,  H01L2924/384 ,  H01Q1/44 ,  H01Q17/00 ,  H01Q23/00 ,  H05K3/3436 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A semiconductor module having one or more integrated antennas in a single package is provided herein. The semiconductor module has a bonding interconnect structure that connects an integrated package to a printed circuit board (PCB), wherein the integrated antenna structures are located at greater center-to-center distance from the IC device than the three dimensional interconnect structures. Therefore, the bonding interconnect structures are confined to a connection area that causes a part of the package containing the one or more antenna structures to extend beyond the bonding interconnect structure as a cantilevered structure. Such a bonding interconnect structure result in a package that is in contact with a PCB at a relatively small area that supports the load of the package.

Abstract translation: 本文提供了在单个封装中具有一个或多个集成天线的半导体模块。 半导体模块具有将集成封装连接到印刷电路板（PCB）的接合互连结构，其中集成天线结构位于距离IC器件比三维互连结构更大的中心到中心距离处。 因此，接合互连结构被限制在连接区域上，该连接区域使得包含一个或多个天线结构的封装的一部分延伸超过作为悬臂结构的接合互连结构。 这种接合互连结构导致在支撑封装负载的较小区域处与PCB接触的封装。

公开(公告)号：US08451618B2

公开(公告)日：2013-05-28

申请号：US12914274

申请日：2010-10-28

Applicant: Josef Boeck ,  Rudolf Lachner ,  Maciej Wojnowski ,  Thorsten Meyer

Inventor： Josef Boeck ,  Rudolf Lachner ,  Maciej Wojnowski ,  Thorsten Meyer

IPC: H05K1/18

CPC classification number: H01L24/20 ,  G01S7/032 ,  H01L23/49816 ,  H01L23/66 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/19 ,  H01L24/32 ,  H01L24/81 ,  H01L24/96 ,  H01L2223/6677 ,  H01L2224/0401 ,  H01L2224/11318 ,  H01L2224/1132 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/1319 ,  H01L2224/13191 ,  H01L2224/13299 ,  H01L2224/14051 ,  H01L2224/141 ,  H01L2224/14505 ,  H01L2224/14517 ,  H01L2224/16225 ,  H01L2224/17517 ,  H01L2224/21 ,  H01L2224/2101 ,  H01L2224/211 ,  H01L2224/215 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81801 ,  H01L2224/831 ,  H01L2924/01029 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/3512 ,  H01L2924/384 ,  H01Q1/44 ,  H01Q17/00 ,  H01Q23/00 ,  H05K3/3436 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A semiconductor module having one or more integrated antennas in a single package is provided herein to comprise a bonding interconnect structure having a plurality of individual bonding elements that are confined to a relatively small area of the bottom of a package. In particular, the semiconductor module comprises a bonding interconnect structure configured to connect an integrated package to a printed circuit board (PCB), wherein the integrated antenna structures are located at greater center-to-center distance from the IC device than the three dimensional interconnect structures. Therefore, the bonding interconnect structures are confined to a connection area that causes a part of the package containing the one or more antenna structures to extend beyond the bonding interconnect structure as a cantilevered structure. Such a bonding interconnect structure result in a package that is in contact with a PCB at a relatively small area that supports the load of the package.

Abstract translation: 本文提供了在单个封装中具有一个或多个集成天线的半导体模块，其包括具有限定在封装的底部的较小区域的多个单独的结合元件的接合互连结构。 特别地，半导体模块包括被配置为将集成封装连接到印刷电路板（PCB）的接合互连结构，其中集成天线结构位于距离IC器件更大的中心到距离三维互连 结构。 因此，接合互连结构被限制在连接区域上，该连接区域使得包含一个或多个天线结构的封装的一部分延伸超过作为悬臂结构的接合互连结构。 这种接合互连结构导致在支撑封装负载的较小区域处与PCB接触的封装。

公开(公告)号：US08138019B2

公开(公告)日：2012-03-20

申请号：US12611285

申请日：2009-11-03

Applicant: Sang Won Yoon ,  Alexandros Margomenos

Inventor： Sang Won Yoon ,  Alexandros Margomenos

IPC: H01L21/00 ,  H01L21/30

CPC classification number: H01L25/0657 ,  B81C1/00238 ,  B81C2203/0771 ,  B81C2203/0792 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/11003 ,  H01L2224/111 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/1148 ,  H01L2224/1184 ,  H01L2224/11845 ,  H01L2224/11849 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1329 ,  H01L2224/13299 ,  H01L2224/133 ,  H01L2224/276 ,  H01L2224/2784 ,  H01L2224/27845 ,  H01L2224/29011 ,  H01L2224/29101 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/30181 ,  H01L2224/73104 ,  H01L2224/811 ,  H01L2224/81903 ,  H01L2224/83101 ,  H01L2224/83203 ,  H01L2224/838 ,  H01L2224/8385 ,  H01L2224/9221 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06562 ,  H01L2225/06565 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07811 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/1579 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/01027 ,  H01L2924/3512

Abstract: A process of forming a semiconductor integrated circuit that includes the steps of: forming at least a first element having a first pattern of conductive material and including a polymer layer surrounding the conductive material, forming at least a second element having a second pattern of conductive material and including a polymer layer surrounding the conductive material, positioning the first element relative to the second element, and bonding the polymer layer of the first and second elements at a temperature below a melting temperature of the conductive materials of the first and second elements wherein the conductive material of the first element contacts the conductive material of the second element and is maintained in position by the bonded polymer layers.

Abstract translation: 一种形成半导体集成电路的方法，包括以下步骤：至少形成具有导电材料的第一图案的第一元件，并且包括围绕导电材料的聚合物层，至少形成具有第二导电材料图案的第二元件 并且包括围绕所述导电材料的聚合物层，相对于所述第二元件定位所述第一元件，以及在低于所述第一和第二元件的导电材料的熔融温度的温度下将所述第一和第二元件的聚合物层粘合，其中 第一元件的导电材料接触第二元件的导电材料，并通过结合的聚合物层保持在适当的位置。