公开(公告)号：US10211142B1

公开(公告)日：2019-02-19

申请号：US15886851

申请日：2018-02-02

申请人： ChipMOS Technologies Inc.

发明人： Pi-Chang Chen ,  Yong-Fang Chiang

IPC分类号： H01L23/498 ,  H01L23/00

摘要： A COF package structure includes a flexible substrate and a chip. A chip mounting area is defined on an upper surface of a flexible base of the flexible substrate. A circuit layer of the flexible substrate includes a plurality of first upper leads, second upper leads, first conductive vias and lower leads. The second upper leads are disposed in the chip mounting area and divided into groups, and each second upper lead has a second inner end and an upper pad opposite to each other. The upper pads of each group are arranged layer by layer into at least two rows. There are two upper pads symmetrically arranged on both sides of a reference line of each group on at least one row furthest from the second inner ends. The first conductive vias connect the upper pads and the lower leads. The chip is mounted in the chip mounting area.

公开(公告)号：US10068861B2

公开(公告)日：2018-09-04

申请号：US15281095

申请日：2016-09-30

申请人： ChipMOS Technologies Inc.

发明人： Kun-Shu Chuang

IPC分类号： H01L23/00 ,  H01L23/498

摘要： Provided is a semiconductor device including a substrate, a pad, a protective layer, a plurality of convex patterns, a redistribution layer (RDL), and a bump. The pad is disposed on the substrate. The protective layer is disposed on the substrate. The protective layer has a first opening exposing a portion of a surface of the pad. The convex patterns are disposed on the protective layer. The RDL is disposed on the convex patterns. The RDL extends from the pad to the convex patterns. The bump is disposed on the convex patterns.

公开(公告)号：US09953960B2

公开(公告)日：2018-04-24

申请号：US15484056

申请日：2017-04-10

申请人： ChipMOS Technologies Inc.

发明人： Shih-Wen Chou

IPC分类号： H01L25/065 ,  H01L21/56 ,  H01L21/78 ,  H01L25/00

CPC分类号： H01L25/0657 ,  H01L21/561 ,  H01L21/563 ,  H01L21/78 ,  H01L23/3142 ,  H01L24/09 ,  H01L24/11 ,  H01L24/17 ,  H01L24/81 ,  H01L24/94 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/06135 ,  H01L2224/1403 ,  H01L2224/14131 ,  H01L2224/14179 ,  H01L2224/16147 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/26145 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/83385 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06568 ,  H01L2224/11 ,  H01L2224/81 ,  H01L2224/03 ,  H01L2224/83

摘要： A multi-chip package structure includes a first chip, at least one blocking structure, a plurality of first conductive bumps, a second chip, a plurality of second conductive bumps and an underfill. The first chip has a chip connecting zone, a plurality of first inner pads in the chip connecting zone and a plurality of first outer pads outside of the chip connecting zone. The blocking structure is disposed between the first inner pads and the first outer pads and surrounds the first inner pads. The first conductive bumps are disposed on the first outer pads. The second chip is flipped on the chip connecting zone and has a plurality of second pads. The second conductive bumps are disposed between the first inner pads and the second pads. The underfill is disposed between the first chip and the second chip so as to cover the second conductive bumps.

公开(公告)号：US09793229B1

公开(公告)日：2017-10-17

申请号：US15455138

申请日：2017-03-10

申请人： ChipMOS Technologies Inc.

发明人： En-Sung Hu

IPC分类号： H01L23/12 ,  H01L21/00 ,  H01L23/00 ,  H01L21/768 ,  H01L21/48 ,  H01L23/48

CPC分类号： H01L24/05 ,  H01L21/4846 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/03 ,  H01L24/11 ,  H01L24/19 ,  H01L2224/02206 ,  H01L2224/02317 ,  H01L2224/0233 ,  H01L2224/0235 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05027 ,  H01L2224/4805

摘要： A re-distribution layer structure is adapted to be disposed on a substrate having a pad and a protective layer which has a first opening exposing a part of the pad. The re-distribution layer structure includes a first and a second patterned insulating layers and a re-distribution layer. The first patterned insulating layer is disposed on the protective layer and includes at least one protrusion and a second opening corresponding to the first opening. The re-distribution layer is disposed on the first patterned insulating layer and includes a pad portion and a wire portion. The pad portion is located on the first patterned insulating layer. The wire portion includes a body and at least one trench caved in the body. The body extends from the pad portion to the pad exposed by the first and the second openings. The body covers the protrusion, and the at least one protrusion extends into the at least one trench. The second patterned insulating layer covers the wire portion and exposes a part of the pad portion. A manufacturing method of re-distribution layer structure is further provided.

公开(公告)号：US20170287801A1

公开(公告)日：2017-10-05

申请号：US15628651

申请日：2017-06-21

申请人： ChipMOS Technologies Inc.

发明人： Shih-Wen Chou

IPC分类号： H01L23/31 ,  H01L23/00 ,  H01L21/56 ,  H01L25/065 ,  H01L25/00

CPC分类号： H01L23/3157 ,  H01L21/561 ,  H01L21/563 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/06135 ,  H01L2224/1403 ,  H01L2224/16147 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/26145 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/83385 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06568 ,  H01L2224/83 ,  H01L2224/81 ,  H01L2224/03 ,  H01L2224/11

摘要： A wafer level chip package manufacturing process is provided. A wafer includes a plurality of first chips and a circuit layer disposed on the first chips, wherein each of the first chips has a chip bonding region, a plurality of first inner pads located in the chip bonding region and a plurality of first outer pads located outside the chip bonding region, the circuit layer includes a plurality of insulating layers, the insulating layers have at least one groove, the groove is disposed between the first inner pads and the first outer pads, and the groove surrounds the first inner pads. A plurality of second chips are flipped on the chip bonding regions, so that second conductive bumps are located between and connected to the first inner pads and second pads of the second chips.

公开(公告)号：US09735132B1

公开(公告)日：2017-08-15

申请号：US15358152

申请日：2016-11-22

申请人： ChipMOS Technologies Inc.

发明人： Cheng-Yu Yang ,  Cheng-Yi Weng

IPC分类号： H01L23/48 ,  H01L25/065 ,  H01L23/00

CPC分类号： H01L25/0657 ,  H01L21/563 ,  H01L24/06 ,  H01L24/10 ,  H01L24/13 ,  H01L24/17 ,  H01L24/26 ,  H01L24/32 ,  H01L2224/0603 ,  H01L2224/06155 ,  H01L2224/06156 ,  H01L2224/06177 ,  H01L2224/10126 ,  H01L2224/10145 ,  H01L2224/13147 ,  H01L2224/13611 ,  H01L2224/1703 ,  H01L2224/17051 ,  H01L2224/17155 ,  H01L2224/17156 ,  H01L2224/17177 ,  H01L2224/26155 ,  H01L2224/26175 ,  H01L2224/3201 ,  H01L2224/32058 ,  H01L2224/32059 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06568

摘要： A semiconductor package includes a first chip, an insulating protection layer, a second chip, a plurality of second conductive bumps and an underfill. The insulating protection layer is disposed on a first active surface of the first chip and includes a concave. Projections of a plurality of first inner pads and a plurality of first outer pads of the first chip projected on the insulating protection layer are located in the concave and out of the concave, respectively. The second chip is flipped on the concave and includes a plurality of second pads. Each of the first inner pads is electrically connected to the corresponding second pad through the corresponding second conductive bump. The underfill is disposed between the concave and the second chip and covers the second conductive bumps.

公开(公告)号：US09401318B2

公开(公告)日：2016-07-26

申请号：US14656631

申请日：2015-03-12

申请人： ChipMOS Technologies Inc.

发明人： Chi-Jin Shih

IPC分类号： H01L23/495 ,  H01L23/00 ,  H01L21/56 ,  H01L21/48 ,  H01L23/31

CPC分类号： H01L23/49503 ,  H01L21/4832 ,  H01L21/4842 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/49541 ,  H01L24/09 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L2224/04042 ,  H01L2224/32245 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45164 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/491 ,  H01L2224/49112 ,  H01L2224/73265 ,  H01L2224/83101 ,  H01L2224/83385 ,  H01L2224/92247 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A quad flat no-lead package includes an encapsulant, and a plurality of chip pads, a plurality of bond pads and a chip disposed in the encapsulant. Each chip pad is connected to at least one of the chip pads adjacent thereto by a first extending portion. The chip pads and the bond pads are arranged in an array. The chip pads are disposed at the center of the array and the bond pads are disposed around the chip pads. Each of the bond pads and at least one of the bond pads or one of the chip pads adjacent thereto each has a second extending portion formed therebetween and corresponding to each other. Every two of the second extending portions corresponding to each other are separated by a groove. The chip is mounted on a top surface of the chip pads and is electrically coupled to the bond pads.

摘要翻译： 四边形无引线封装包括密封剂和多个芯片焊盘，多个焊盘和设置在密封剂中的芯片。 每个芯片焊盘通过第一延伸部连接到与其相邻的至少一个芯片焊盘。 芯片焊盘和接合焊盘被布置成阵列。 芯片焊盘设置在阵列的中心，并且接合焊盘设置在芯片焊盘周围。 每个接合焊盘和至少一个接合焊盘或与其相邻的芯片焊盘之一每个都具有形成在它们之间并相互对应的第二延伸部分。 彼此对应的每两个第二延伸部分被凹槽分开。 芯片安装在芯片焊盘的顶表面上，并且电耦合到焊盘。

公开(公告)号：US20150303133A1

公开(公告)日：2015-10-22

申请号：US14619257

申请日：2015-02-11

申请人： ChipMOS Technologies Inc.

发明人： Chi-Jin SHIH

IPC分类号： H01L23/495 ,  H01L23/00 ,  H01L21/56 ,  H01L23/28

CPC分类号： H01L23/49503 ,  H01L21/56 ,  H01L23/28 ,  H01L23/3107 ,  H01L23/49541 ,  H01L23/49551 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/491 ,  H01L2224/49109 ,  H01L2224/49112 ,  H01L2224/73265 ,  H01L2224/8385 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012

摘要： A flat no-lead package includes an encapsulating material, and a die pad, a chip, a plurality of first contact pads and a plurality of second contact pads disposed in the encapsulating material. The encapsulating material has a package bottom surface. The die pad has a plurality of die pad extensions extending from the edges thereof. The chip is mounted on the die pad. The first contact pads are disposed near the edges of the encapsulating material and electrically coupled to the chip. The second contact pads are located between the die pad and the first contact pads and electrically coupled to the chip. Each of the second contact pads have a second contact pad extension corresponding to one of the die pad extensions respectively. The bottom surfaces of the first contact pads, the second contact pads and the second contact pad extensions arc exposed on the package bottom surface,

摘要翻译： 扁平无引线封装包括封装材料，以及管芯焊盘，芯片，多个第一接触焊盘和设置在封装材料中的多个第二接触焊盘。 封装材料具有封装底表面。 管芯焊盘具有从其边缘延伸的多个管芯焊盘延伸部。 芯片安装在芯片上。 第一接触垫设置在封装材料的边缘附近并电耦合到芯片。 第二接触焊盘位于管芯焊盘和第一接触焊盘之间并且电耦合到芯片。 每个第二接触焊盘具有分别对应于一个管芯焊盘延伸部的第二接触焊盘延伸部。 第一接触焊盘的底表面，第二接触焊盘和第二接触焊盘延伸部暴露在封装底表面上，

公开(公告)号：US20150236245A1

公开(公告)日：2015-08-20

申请号：US14553371

申请日：2014-11-25

申请人： ChipMOS Technologies, Inc.

发明人： Shih-Wen CHOU

IPC分类号： H01L43/02 ,  H01L43/12 ,  H01L43/08

CPC分类号： H01L43/02 ,  H01L43/08 ,  H01L2224/32245 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/00

摘要： A semiconductor package and manufacturing method thereof are disclosed. The semiconductor package includes a package carrier, a chip, a film, a first shielding metal plate and an encapsulating material. The package carrier has at least one conductive component. The chip has an active surface and a corresponding back surface. The back surface of the chip is attached to the package carrier. At least one contact point is disposed on the active surface and is electrically coupled to the conductive component by a wire. The film is disposed on the active surface and covers a portion of the wire. The first shielding metal plate is disposed on the film. The encapsulating material covers the chip, the wire, at least one portion of the package carrier, the film and at least one portion of the first shielding metal plate.

摘要翻译： 公开了半导体封装及其制造方法。 半导体封装包括封装载体，芯片，膜，第一屏蔽金属板和封装材料。 封装载体具有至少一个导电部件。 该芯片具有活性表面和相应的背面。 芯片的背面附着在封装载体上。 至少一个接触点设置在有源表面上并且通过导线电耦合到导电部件。 该膜设置在有源表面上并覆盖该线的一部分。 第一屏蔽金属板设置在膜上。 封装材料覆盖芯片，导线，封装载体的至少一部分，薄膜以及第一屏蔽金属板的至少一部分。

公开(公告)号：US20150130084A1

公开(公告)日：2015-05-14

申请号：US14246302

申请日：2014-04-07

申请人： CHIPMOS TECHNOLOGIES INC.

发明人： TSUNG JEN LIAO

IPC分类号： H01L23/00 ,  H01L21/306 ,  H01L23/36

CPC分类号： H01L21/30604 ,  H01L21/6836 ,  H01L23/3114 ,  H01L23/3192 ,  H01L23/3677 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/525 ,  H01L24/02 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L24/94 ,  H01L29/0657 ,  H01L2221/6834 ,  H01L2224/0231 ,  H01L2224/0235 ,  H01L2224/02351 ,  H01L2224/0236 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/0239 ,  H01L2224/0332 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05166 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05569 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/11418 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13027 ,  H01L2224/131 ,  H01L2224/94 ,  H01L2924/01022 ,  H01L2924/10156 ,  H01L2924/10157 ,  H01L2924/10158 ,  H05K1/111 ,  H05K2201/09436 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/01074 ,  H01L2924/00014 ,  H01L2224/03 ,  H01L2224/11

摘要： A fan-out package structure including a heat radiating side edge that includes a semiconductor substrate; a bond pad located on the semiconductor substrate; and a redistribution layer connected with the bond pad and located on the semiconductor substrate, wherein an end of the redistribution layer extends to a sidewall of the semiconductor substrate, and the end is coplanar with the sidewall.

摘要翻译： 一种包括散热侧边缘的扇出封装结构，包括半导体衬底; 位于所述半导体衬底上的接合焊盘; 以及再结合层，其与所述接合焊盘连接并且位于所述半导体衬底上，其中所述再分布层的端部延伸到所述半导体衬底的侧壁，并且所述端部与所述侧壁共面。