公开(公告)号：US20200321196A1

公开(公告)日：2020-10-08

申请号：US16908214

申请日：2020-06-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chang-Yin CHEN ,  Tung-Wen CHENG ,  Che-Cheng CHANG ,  Jr-Jung LIN ,  Chih-Han LIN

IPC: H01J37/32 ,  H01L21/8234 ,  H01L21/3213 ,  H01L29/66 ,  H01L29/78 ,  H01L21/67

Abstract: A dry etching apparatus includes a process chamber, a stage, a gas supply device and a plasma generating device. The stage is in the process chamber and is configured to support a wafer, wherein the wafer has a center region and a periphery region surrounding the center region. The gas supply device is configured to supply a first flow of an etching gas to the center region and supply a second flow of the etching gas to the periphery region. The plasma generating device is configured to generate plasma from the etching gas.

公开(公告)号：US20160148935A1

公开(公告)日：2016-05-26

申请号：US14554682

申请日：2014-11-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Yin CHEN ,  Tung-Wen CHENG ,  Che-Cheng CHANG ,  Chun-Lung NI ,  Jr-Jung LIN ,  Chih-Han LIN

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/51 ,  H01L21/033 ,  H01L21/8238 ,  H01L21/8234 ,  H01L21/02 ,  H01L21/311 ,  H01L27/088 ,  H01L29/49

CPC classification number: H01L21/0338 ,  H01L21/0206 ,  H01L21/0212 ,  H01L21/02274 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823878 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

Abstract: A fin field effect transistor (FinFET) device structure and method for forming FinFET device structure is provided. The FinFET device structure includes a substrate and a first fin structure and a second fin structure extending above the substrate. The FinFET device structure also includes a first transistor formed on the first fin structure and a second transistor formed on the second fin structure. The FinFET device structure further includes an inter-layer dielectric (ILD) structure formed in an end-to-end gap between the first transistor and the second transistor, and the end-to-end gap has a width in a range from about 20 nm to about 40 nm.

Abstract translation: 提供了一种用于形成FinFET器件结构的鳍式场效应晶体管（FinFET）器件结构和方法。 FinFET器件结构包括衬底和在衬底上方延伸的第一鳍结构和第二鳍结构。 FinFET器件结构还包括形成在第一鳍结构上的第一晶体管和形成在第二鳍结构上的第二晶体管。 FinFET器件结构还包括形成在第一晶体管和第二晶体管之间的端到端间隙中的层间电介质（ILD）结构，并且端对端间隙具有在约20° nm至约40nm。

公开(公告)号：US20150115363A1

公开(公告)日：2015-04-30

申请号：US14067424

申请日：2013-10-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD

Inventor： Che-Cheng CHANG ,  Chang-Yin CHEN ,  Jr-Jung LIN ,  Chih-Han LIN ,  Yung-Jung CHANG

IPC: H01L27/12 ,  H01L21/306 ,  H01L21/8234

CPC classification number: H01L27/1211 ,  H01L21/32137 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0886

Abstract: Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a substrate. The semiconductor device also includes a first fin and a second fin over the substrate. The semiconductor device further includes a first gate electrode and a second gate electrode traversing over the first fin and the second fin, respectively. In addition, the semiconductor device includes a gate dielectric layer between the first fin and the first gate electrode and between the second fin and the second gate electrode. Further, the semiconductor device includes a dummy gate electrode over the substrate, and the dummy gate electrode is between the first gate electrode and the second gate electrode. An upper portion of the dummy gate electrode is wider than a lower portion of the dummy gate electrode.

Abstract translation: 提供了用于形成半导体器件的机构的实施例。 半导体器件包括衬底。 半导体器件还包括在衬底上的第一鳍和第二鳍。 半导体器件还包括分别在第一鳍片和第二鳍片上横穿的第一栅极电极和第二栅极电极。 此外，半导体器件包括在第一鳍片和第一栅极电极之间以及第二鳍片和第二栅极电极之间的栅极电介质层。 此外，半导体器件在衬底上包括虚拟栅电极，并且虚设栅极位于第一栅电极和第二栅电极之间。 虚拟栅电极的上部比虚拟栅电极的下部宽。

公开(公告)号：US20160111541A1

公开(公告)日：2016-04-21

申请号：US14517272

申请日：2014-10-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng CHANG ,  Chih-Han LIN ,  Jr-Jung LIN

IPC: H01L29/78 ,  H01L21/3213 ,  H01L21/311 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L21/31144 ,  H01L21/31111 ,  H01L21/32133 ,  H01L21/32137 ,  H01L29/66545 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate and a metal gate structure formed over a fin structure of the substrate. The semiconductor structure further includes a spacer formed on a sidewall of the metal gate structure and a source/drain structure formed in the fin structure. In addition, the spacer is in direct contact with the fin structure.

Abstract translation: 提供半导体结构及其形成方法。 半导体结构包括在基板的翅片结构上形成的基板和金属栅极结构。 半导体结构还包括形成在金属栅极结构的侧壁上的隔离物和形成在鳍结构中的源极/漏极结构。 此外，间隔件与翅片结构直接接触。

公开(公告)号：US20150236132A1

公开(公告)日：2015-08-20

申请号：US14181320

申请日：2014-02-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng CHANG ,  Chang-Yin CHEN ,  Jr-Jung LIN ,  Chih-Han LIN ,  Yung-Jung CHANG

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/7848 ,  H01L29/785

Abstract: Embodiments for forming a fin field effect transistor (FinFET) device structure are provided. The FinFET device structure includes a fin structure extending above a substrate and a gate dielectric layer formed over the fin structure. The FinFET device structure also includes a gate electrode formed on the gate dielectric layer. The FinFET device structure further includes a number of gate spacers formed on sidewalls of the gate electrode. The gate spacers are in direct contact with the fin structure.

Abstract translation: 提供了用于形成鳍状场效应晶体管（FinFET）器件结构的实施例。 FinFET器件结构包括在衬底上延伸的翅片结构和形成在鳍结构上的栅极电介质层。 FinFET器件结构还包括形成在栅极介电层上的栅电极。 FinFET器件结构还包括形成在栅电极的侧壁上的多个栅极间隔物。 栅极间隔件与翅片结构直接接触。

公开(公告)号：US20190288084A1

公开(公告)日：2019-09-19

申请号：US15920866

申请日：2018-03-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ricky WANG ,  Chao-Cheng CHEN ,  Jr-Jung LIN ,  Chi-Wei YANG

IPC: H01L29/423 ,  H01L29/78 ,  H01L21/3213

Abstract: Semiconductor device structures comprising a gate structure having different profiles at different portions of the gate structure are provided. In some examples, a semiconductor device includes a fin structure on a substrate, a source/drain structure on the fin structure, and a gate structure over the fin structure and along a sidewall of the fin. The source/drain structure is proximate the gate structure. The gate structure has a top portion having a first sidewall profile and a bottom portion having a second sidewall profile different from the first sidewall profile.

公开(公告)号：US20160240537A1

公开(公告)日：2016-08-18

申请号：US14698831

申请日：2015-04-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng CHANG ,  Jr-Jung LIN ,  Chih-Han LIN

IPC: H01L27/092 ,  H01L29/16 ,  H01L29/161 ,  H01L29/06 ,  H01L29/66 ,  H01L21/306 ,  H01L21/8238 ,  H01L29/165 ,  H01L29/78

CPC classification number: H01L29/7848 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66795

Abstract: A semiconductor device includes a Fin FET transistor. The Fin FET transistor includes a first fin structure extending in a first direction, a gate stack and a source and a drain. The gate stack includes a gate electrode layer and a gate dielectric layer, covers a portion of the fin structure and extends in a second direction perpendicular to the first direction. Each of the source and drain includes a stressor layer disposed over the fin structure. The stressor layer applies a stress to a channel layer of the fin structure under the gate stack. The stressor layer penetrates under the gate stack. A vertical interface between the stressor layer and the fin structure under the gate stack in a third direction perpendicular to the first and second directions includes a flat portion.

Abstract translation: 半导体器件包括Fin FET晶体管。 鳍式FET晶体管包括沿第一方向延伸的第一鳍状结构，栅极堆叠以及源极和漏极。 栅堆叠包括栅极电极层和栅极电介质层，覆盖翅片结构的一部分并且沿垂直于第一方向的第二方向延伸。 源极和漏极中的每一个包括设置在鳍结构上的应力层。 应力层对栅叠层下的鳍结构的沟道层施加应力。 应力层穿过栅极叠层。 在垂直于第一和第二方向的第三方向上的应力层和翅片结构之间的垂直界面包括平坦部分。

公开(公告)号：US20190043763A1

公开(公告)日：2019-02-07

申请号：US15670401

申请日：2017-08-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Cheng LI ,  Chien-Hao CHEN ,  Yung-Cheng LU ,  Jr-Jung LIN ,  Chun-Hung LEE ,  Chao-Cheng CHEN

IPC: H01L21/8238 ,  H01L21/28 ,  H01L27/108 ,  H01L29/66 ,  H01L27/092

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first amorphous layer over a substrate. The substrate has a base portion and a first fin portion over the base portion, and the first amorphous layer covers the first fin portion. The method includes annealing the first amorphous layer to crystallize the first amorphous layer into a first polycrystalline layer. The method includes forming a second amorphous layer over the first polycrystalline layer. The method includes removing a first portion of the second amorphous layer and a second portion of the first polycrystalline layer under the first portion. The remaining second amorphous layer and the remaining first polycrystalline layer together form a first gate structure over and across the first fin portion.

公开(公告)号：US20170186588A1

公开(公告)日：2017-06-29

申请号：US15460771

申请日：2017-03-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chang-Yin CHEN ,  Tung-Wen CHENG ,  Che-Cheng CHANG ,  Jr-Jung LIN ,  Chih-Han LIN

IPC: H01J37/32 ,  H01L21/8234 ,  H01L21/3213 ,  H01L21/67

Abstract: A dry etching apparatus includes a process chamber, a stage, a gas supply device and a plasma generating device. The stage is in the process chamber and is configured to support a wafer, wherein the wafer has a center region and a periphery region surrounding the center region. The gas supply device is configured to supply a first flow of an etching gas to the center region and supply a second flow of the etching gas to the periphery region. The plasma generating device is configured to generate plasma from the etching gas.

公开(公告)号：US20160322498A1

公开(公告)日：2016-11-03

申请号：US15208377

申请日：2016-07-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng CHANG ,  Jr-Jung LIN ,  Chih-Han LIN

IPC: H01L29/78 ,  H01L29/165 ,  H01L29/16 ,  H01L29/161 ,  H01L27/092 ,  H01L29/66 ,  H01L21/02 ,  H01L21/306 ,  H01L21/8238 ,  H01L29/08 ,  H01L27/088 ,  H01L29/06

CPC classification number: H01L29/7848 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66795

Abstract: A semiconductor device includes a Fin FET transistor. The Fin FET transistor includes a first fin structure extending in a first direction, a gate stack and a source and a drain. The gate stack includes a gate electrode layer and a gate dielectric layer, covers a portion of the fin structure and extends in a second direction perpendicular to the first direction. Each of the source and drain includes a stressor layer disposed over the fin structure. The stressor layer applies a stress to a channel layer of the fin structure under the gate stack. The stressor layer penetrates under the gate stack. A vertical interface between the stressor layer and the fin structure under the gate stack in a third direction perpendicular to the first and second directions includes a flat area, and the flat area extends in the second direction and the third direction.

Abstract translation: 半导体器件包括Fin FET晶体管。 鳍FET晶体管包括沿第一方向延伸的第一鳍结构，栅极堆叠以及源极和漏极。 栅堆叠包括栅极电极层和栅极电介质层，覆盖翅片结构的一部分并且沿垂直于第一方向的第二方向延伸。 源极和漏极中的每一个包括设置在鳍结构上的应力层。 应力层对栅叠层下的鳍结构的沟道层施加应力。 应力层穿过栅极叠层。 在垂直于第一和第二方向的第三方向上，在堆叠堆叠处的应力层和翅片结构之间的垂直界面包括平坦区域，并且平坦区域在第二方向和第三方向上延伸。