公开(公告)号：US20230387245A1

公开(公告)日：2023-11-30

申请号：US18232191

申请日：2023-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Liang LU ,  Chang-Yin CHEN ,  Chih-Han LIN ,  Chia-Yang LIAO

IPC: H01L29/49 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/8238

CPC classification number: H01L29/4983 ,  H01L29/0847 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7851 ,  H01L21/823864 ,  H01L29/785 ,  H01L27/0886 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823821 ,  H01L29/66545

Abstract: A semiconductor device and methods of fabricating the same are disclosed. The semiconductor device includes a substrate, a fin structure with a fin top surface disposed on the substrate, a source/drain (S/D) region disposed on the fin structure, a gate structure disposed on the fin top surface, and a gate spacer with first and second spacer portions disposed between the gate structure and the S/D region. The first spacer portion extends above the fin top surface and is disposed along a sidewall of the gate structure. The second spacer portion extends below the fin top surface and is disposed along a sidewall of the S/D region.

公开(公告)号：US20220199413A1

公开(公告)日：2022-06-23

申请号：US17692824

申请日：2022-03-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chang-Yin CHEN ,  Che-Cheng CHANG ,  Chih-Han LIN

IPC: H01L21/308 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/78

Abstract: A method includes following steps. A substrate is etched using a hard mask as an etch mask to form a fin. A bottom anti-reflective coating (BARC) layer is over the fin. A recess is formed in the BARC layer to expose a first portion of the hard mask. A protective coating layer is formed at least on a sidewall of the recess in the BARC layer. A first etching step is performed to remove the first portion of the hard mask to expose a first portion of the fin, while leaving a second portion of the fin covered under the protective coating layer and the BARC layer. A second etching step is performed to lower a top surface of the first portion of the fin to below a top surface of the second portion of the fin.

公开(公告)号：US20200321196A1

公开(公告)日：2020-10-08

申请号：US16908214

申请日：2020-06-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chang-Yin CHEN ,  Tung-Wen CHENG ,  Che-Cheng CHANG ,  Jr-Jung LIN ,  Chih-Han LIN

IPC: H01J37/32 ,  H01L21/8234 ,  H01L21/3213 ,  H01L29/66 ,  H01L29/78 ,  H01L21/67

Abstract: A dry etching apparatus includes a process chamber, a stage, a gas supply device and a plasma generating device. The stage is in the process chamber and is configured to support a wafer, wherein the wafer has a center region and a periphery region surrounding the center region. The gas supply device is configured to supply a first flow of an etching gas to the center region and supply a second flow of the etching gas to the periphery region. The plasma generating device is configured to generate plasma from the etching gas.

公开(公告)号：US20180040735A1

公开(公告)日：2018-02-08

申请号：US15788803

申请日：2017-10-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng CHANG ,  Tung-Wen CHENG ,  Chang-Yin CHEN ,  Mu-Tsang LIN

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/51 ,  H01L29/49 ,  H01L21/3213 ,  H01L29/08 ,  H01L21/3105 ,  H01L21/306 ,  H01L29/66 ,  H01L29/423 ,  H01L29/165 ,  H01L21/311

CPC classification number: H01L29/7851 ,  H01L21/0223 ,  H01L21/02255 ,  H01L21/30604 ,  H01L21/31055 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/31144 ,  H01L21/32133 ,  H01L21/32136 ,  H01L21/32139 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/42368 ,  H01L29/495 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7848

Abstract: A semiconductor structure and a method of fabricating the semiconductor structure are provided. The semiconductor structure includes a substrate; a metal gate structure on the substrate; and a spacer next to the metal gate structure having a skirting part extending into the metal gate structure and contacting the substrate. The metal gate structure includes a high-k dielectric layer and a metal gate electrode on the high-k dielectric layer.

公开(公告)号：US20160148935A1

公开(公告)日：2016-05-26

申请号：US14554682

申请日：2014-11-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Yin CHEN ,  Tung-Wen CHENG ,  Che-Cheng CHANG ,  Chun-Lung NI ,  Jr-Jung LIN ,  Chih-Han LIN

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/51 ,  H01L21/033 ,  H01L21/8238 ,  H01L21/8234 ,  H01L21/02 ,  H01L21/311 ,  H01L27/088 ,  H01L29/49

CPC classification number: H01L21/0338 ,  H01L21/0206 ,  H01L21/0212 ,  H01L21/02274 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823878 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

Abstract: A fin field effect transistor (FinFET) device structure and method for forming FinFET device structure is provided. The FinFET device structure includes a substrate and a first fin structure and a second fin structure extending above the substrate. The FinFET device structure also includes a first transistor formed on the first fin structure and a second transistor formed on the second fin structure. The FinFET device structure further includes an inter-layer dielectric (ILD) structure formed in an end-to-end gap between the first transistor and the second transistor, and the end-to-end gap has a width in a range from about 20 nm to about 40 nm.

Abstract translation: 提供了一种用于形成FinFET器件结构的鳍式场效应晶体管（FinFET）器件结构和方法。 FinFET器件结构包括衬底和在衬底上方延伸的第一鳍结构和第二鳍结构。 FinFET器件结构还包括形成在第一鳍结构上的第一晶体管和形成在第二鳍结构上的第二晶体管。 FinFET器件结构还包括形成在第一晶体管和第二晶体管之间的端到端间隙中的层间电介质（ILD）结构，并且端对端间隙具有在约20° nm至约40nm。

公开(公告)号：US20210013045A1

公开(公告)日：2021-01-14

申请号：US17018479

申请日：2020-09-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chang-Yin CHEN ,  Che-Cheng CHANG ,  Chih-Han LIN

IPC: H01L21/308 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/78

Abstract: A first semiconductor fin and a second semiconductor fin are disposed over a substrate. The second semiconductor fin and the first semiconductor fin are aligned substantially along a same line and spaced apart from each other. The first semiconductor fin has a first end portion, the second semiconductor fin has a second end portion, and an end sidewall of the first end portion and is spaced apart from an end sidewall of the second end portion. The gate structure extends substantially perpendicularly to the first semiconductor fin. When viewed from above, the gate structure overlaps with the first end portion of the first semiconductor fin. When viewed from above, the end sidewall of the first end portion of the first semiconductor fin facing the end sidewall of the second end portion of the second semiconductor fin has a re-entrant profile.

公开(公告)号：US20200328286A1

公开(公告)日：2020-10-15

申请号：US16914940

申请日：2020-06-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chang-Yin CHEN ,  Che-Cheng CHANG ,  Chih-Han LIN

IPC: H01L29/49 ,  H01L29/66 ,  H01L21/28

Abstract: A method of forming a semiconductor structure includes forming a dummy gate feature over a semiconductive fin; forming a first spacer around the dummy gate feature and a second spacer around the first spacer; replacing the dummy gate feature with a metal gate feature; after replacing the dummy gate feature with the metal gate feature, partially removing the second spacer such that a top of the second spacer is lower than a top of the first spacer; and depositing a capping layer over and in contact with the metal gate feature and the first spacer.

公开(公告)号：US20170005005A1

公开(公告)日：2017-01-05

申请号：US14942491

申请日：2015-11-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Yin CHEN ,  Chai-Wei CHANG ,  Yi-Jen CHEN ,  Bo-Feng YOUNG

IPC: H01L21/8234 ,  H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L27/088 ,  H01L21/283 ,  H01L21/31 ,  H01L21/311 ,  H01L21/3213 ,  H01L29/78 ,  H01L21/762

CPC classification number: H01L21/823437 ,  H01L21/32137 ,  H01L21/762 ,  H01L21/823431 ,  H01L21/823462 ,  H01L27/0886 ,  H01L29/42376 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/785

Abstract: A FinFET device structure and method for forming the same are provided. The FinFET device structure includes a fin structure formed over a substrate and a gate structure traversing over the fin structure. The gate structure includes a gate electrode layer which includes an upper portion above the fin structure and a lower portion below the fin structure, the virtual surface is formed between the upper portion and the lower portion, and the lower portion has a tapered width which is gradually tapered from the virtual interface to a bottom surface of the lower portion.

Abstract translation: 提供了一种FinFET器件结构及其形成方法。 FinFET器件结构包括在衬底上形成的翅片结构和横过翅片结构的栅极结构。 栅极结构包括栅极电极层，其包括鳍状结构上方的上部和翅片结构下方的下部，虚拟表面形成在上部和下部之间，下部具有锥形宽度， 从虚拟界面逐渐变细到下部的底面。

公开(公告)号：US20210111266A1

公开(公告)日：2021-04-15

申请号：US17129253

申请日：2020-12-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chang-Yin CHEN ,  Che-Cheng CHANG ,  Chih-Han LIN

IPC: H01L29/49 ,  H01L29/66 ,  H01L21/28

Abstract: A device includes a semiconductive fin having source and drain regions and a channel region between the source and drain regions, a gate feature over the channel region of the semiconductive fin, a first spacer around the gate feature, source and drain features respectively in the source and drain regions of the semiconductive fin, an interlayer dielectric layer around the first spacer, and a void between the first spacer and the interlayer dielectric layer and spaced apart from the gate feature and the source and drain features.

公开(公告)号：US20210074840A1

公开(公告)日：2021-03-11

申请号：US16562406

申请日：2019-09-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chang-Yin CHEN ,  Che-Cheng CHANG ,  Chih-Han LIN

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L21/02

Abstract: A semiconductor device includes an isolation insulating layer disposed over a substrate, a semiconductor fin disposed over the substrate, an upper portion of the semiconductor fin protruding from the isolation insulating layer and a lower portion of the semiconductor fin being embedded in the isolation insulating layer, a gate structure disposed over the upper portion of the semiconductor fin and including a gate dielectric layer and a gate electrode layer, gate sidewall spacers disposed over opposing side faces of the gate structure, and a source/drain epitaxial layer. The upper portion of the semiconductor fin includes a first epitaxial growth enhancement layer made of a semiconductor material different from a remaining part of the semiconductor fin. The first epitaxial growth enhancement layer is in contact with the source/drain epitaxial layer. The gate dielectric layer covers the upper portion of the semiconductor fin including the first epitaxial growth enhancement layer.