公开(公告)号：US20250107207A1

公开(公告)日：2025-03-27

申请号：US18974319

申请日：2024-12-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Sheng LAI ,  Wei-Chung SUN ,  Yu-Bey WU ,  Yuan-Ching PENG ,  Yu-Shan LU ,  Li-Ting CHEN ,  Shih-Yao LIN ,  Yu-Fan PENG ,  Kuei-Yu KAO ,  Chih-Han LIN ,  Jing Yi YAN ,  Pei-Yi LIU

IPC: H01L29/423 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

Abstract: A semiconductor structure includes a semiconductor substrate; fin active regions protruded above the semiconductor substrate; and a gate stack disposed on the fin active regions; wherein the gate stack includes a high-k dielectric material layer, and various metal layers disposed on the high-k dielectric material layer. The gate stack has an uneven profile in a sectional view with a first dimension D1 at a top surface, a second dimension D2 at a bottom surface, and a third dimension D3 at a location between the top surface and the bottom surface, and wherein each of D1 and D2 is greater than D3.

公开(公告)号：US20230261111A1

公开(公告)日：2023-08-17

申请号：US18304787

申请日：2023-04-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng CHANG ,  Chih-Han LIN ,  Horng-Huei TSENG

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/3213 ,  H01L21/762 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L21/0228 ,  H01L21/3065 ,  H01L21/32135 ,  H01L21/76243 ,  H01L21/76283 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/66795

Abstract: A device includes a semiconductive substrate, a stop layer, a semiconductive fin, a fin isolation structure, and a source/drain epitaxial layer. The stop layer is over the semiconductive substrate and includes SiGeOx, SiGe, SiP or SiPOx, where x is greater than 0. The semiconductive fin is over the stop layer. The fin isolation structure is connected to a sidewall of the semiconductive fin. The source/drain epitaxial layer is adjacent to the semiconductive fin. The semiconductive fin is between the source/drain epitaxial layer and the fin isolation structure.

公开(公告)号：US20210050447A1

公开(公告)日：2021-02-18

申请号：US16948039

申请日：2020-08-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng CHANG ,  Chih-Han LIN

IPC: H01L29/78 ,  H01L21/8234 ,  H01L21/28 ,  H01L21/283 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66

Abstract: A FinFET device structure and method for forming the same are provided. The FinFET device structure includes a stop layer formed over a substrate and a fin structure formed over the stop layer. The FinFET device structure includes a gate structure formed over the fin structure and a source/drain (S/D) structure adjacent to the gate structure. A bottom surface of the S/D structure is located at a position that is higher than or level with a bottom surface of the stop layer.

公开(公告)号：US20200135481A1

公开(公告)日：2020-04-30

申请号：US16243242

申请日：2019-01-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chang-Yin CHEN ,  Che-Cheng CHANG ,  Chih-Han LIN

IPC: H01L21/308 ,  H01L27/088 ,  H01L21/8234

Abstract: A fin strip is formed over a substrate using a hardmask. The fin strip includes a first portion and a second portion laterally adjoining the first portion. A BARC layer is formed to cover the fin strip over the substrate. A first etching operation is performed to remove a first portion of the BARC layer, so as to expose a portion of the hardmask where the first portion of the fin strip underlies. A coating layer is deposited over the portion of the hardmask and the BARC layer. A second etching operation is performed to remove a portion of the coating layer, the portion of the hardmask and a second portion of the BARC layer. A third etching operation is performed to remove the first portion of the fin strip and a remaining BARC layer, such that the second portion of the fin strip forms a plurality of semiconductor fins.

公开(公告)号：US20190386114A1

公开(公告)日：2019-12-19

申请号：US16007885

申请日：2018-06-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-An LIU ,  Chan-Lon YANG ,  Bharath Kumar PULICHERLA ,  Zhi-Qiang WU ,  Chung-Cheng WU ,  Chih-Han LIN ,  Gwan-Sin CHANG

IPC: H01L29/66 ,  H01L27/088 ,  H01L29/423 ,  H01L21/8234 ,  H01L21/02 ,  H01L21/3213 ,  H01L21/311

Abstract: A semiconductor structure is disclosed that includes the fin structure and the plurality of gates. The plurality of gates disposed with respect to the fin structure and including the first gate, the second gate, and the third gate. The spacing between the first gate and the second gate is smaller than the spacing between the second gate and the third gate. The second gate is disposed between the first gate and the third gate. The foot portion of the first gate, facing the second gate, and the first foot portion of the second gate, facing the first gate, have no lateral extension. The second foot portion of the second gate, facing the third gate, and the foot portion of the third gate, facing the second gate, have no lateral extension and/or cut.

公开(公告)号：US20180350990A1

公开(公告)日：2018-12-06

申请号：US16041664

申请日：2018-07-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng CHANG ,  Chih-Han LIN

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/51 ,  H01L29/423

Abstract: A method includes forming an insulating structure over a substrate, wherein the substrate has a semiconductor fin separated from the insulating structure; depositing a high-κ dielectric layer over the semiconductor fin and a sidewall of the insulating structure facing the semiconductor fin; etching a first portion of the high-κ dielectric layer over the sidewall of the insulating structure, wherein a second portion of the high-κ dielectric layer remains over the semiconductor fin; and depositing a gate electrode over the second portion of the high-κ dielectric layer.

公开(公告)号：US20180204718A1

公开(公告)日：2018-07-19

申请号：US15921624

申请日：2018-03-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng CHANG ,  Chih-Han LIN ,  Horng-Huei TSENG

IPC: H01L21/02 ,  H01L21/306 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/02068 ,  H01L21/30604 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A device includes a fin structure, a dielectric layer, a gate a spacer, and an epitaxy structure. The dielectric layer is over the fin structure. The gate is over the dielectric layer. The spacer is on a sidewall of the gate. The spacer has a thickness along a direction parallel to a longitudinal axis of the fin structure, and a distance along the direction from an outer sidewall of the spacer to an end surface of the fin structure is greater than the thickness of the spacer. The epitaxy structure is in contact with the fin structure.

公开(公告)号：US20180040613A1

公开(公告)日：2018-02-08

申请号：US15227207

申请日：2016-08-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng CHANG ,  Chih-Han LIN ,  Horng-Huei TSENG

IPC: H01L27/088 ,  H01L29/66 ,  H01L29/06 ,  H01L21/8234 ,  H01L23/31 ,  H01L27/02

Abstract: Structures and formation methods of a semiconductor device are provided. The semiconductor device includes a substrate and a first fin structure and a second fin structure over the substrate. The semiconductor device also includes a first gate stack and a second gate stack partially covering the first fin structure and the second fin structure, respectively, and a stack structure over the substrate. The stack structure is between the first gate stack and the second gate stack. The stack structure includes a semiconductor layer over the substrate and a protection layer over the semiconductor layer.

公开(公告)号：US20170179242A1

公开(公告)日：2017-06-22

申请号：US15051619

申请日：2016-02-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng CHANG ,  Chih-Han LIN ,  Horng-Huei TSENG

IPC: H01L29/417 ,  H01L21/311 ,  H01L29/40

CPC classification number: H01L29/4991 ,  H01L21/31111 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/401 ,  H01L29/41775 ,  H01L29/41791 ,  H01L29/515 ,  H01L2221/1042

Abstract: A semiconductor structure includes a substrate, at least one first gate structure, at least one source drain structure, at least one bottom conductor, and a first dielectric layer. The first gate structure is present on the substrate. The source drain structure is present on the substrate. The bottom conductor is electrically connected to the source drain structure. The bottom conductor has an upper portion and a lower portion between the upper portion and the source drain structure, and a gap is at least present between the upper portion of the bottom conductor and the first gate structure. The first dielectric layer is at least present between the lower portion of the bottom conductor and the first gate structure.

公开(公告)号：US20170133501A1

公开(公告)日：2017-05-11

申请号：US14935115

申请日：2015-11-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng CHANG ,  Chih-Han LIN ,  Horng-Huei TSENG

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/3213 ,  H01L29/06 ,  H01L21/762

CPC classification number: H01L29/785 ,  H01L21/0228 ,  H01L21/3065 ,  H01L21/32135 ,  H01L21/76243 ,  H01L21/76283 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/66795

Abstract: A semiconductor device includes a semiconductor device and a semiconductor fin on the semiconductor substrate, in which the semiconductor fin has a fin isolation structure at a common boundary that is shared by the two cells. The fin isolation structure has a dielectric portion extending from a top of the semiconductor fin to a stop layer on the semiconductor substrate. The dielectric portion divides the semiconductor fin into two portions of the semiconductor fin.