公开(公告)号：US20170194243A1

公开(公告)日：2017-07-06

申请号：US15178115

申请日：2016-06-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Bey WU ,  Dian-Hau CHEN ,  Jye-Yen CHENG ,  Sheng-Hsuan WEI ,  Pei-Ru LEE ,  Tai-Yang WU

IPC: H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  G06F17/50 ,  H01L21/768 ,  H01L21/311

CPC classification number: H01L23/528 ,  G06F17/5072 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76877 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/5329

Abstract: A semiconductor device includes a first interlayer dielectric layer disposed over a substrate, metal wirings, a second interlayer dielectric layer disposed over the first interlayer dielectric layer and the metal wirings, a first air gap and a second air gap. The metal wirings are embedded in the first interlayer dielectric layer, and arranged with a first space or a second space between the metal wirings. The second space has a greater length than the first space. The first air gap is formed by the second interlayer dielectric layer and formed in a first area sandwiched by adjacent two metal wirings arranged with the first space. The second air gap is formed by the second interlayer dielectric layer and formed in a second area sandwiched by adjacent two metal wirings arranged with the second space therebetween. No adjacent two metal wirings are arranged with a space smaller than the first space.

公开(公告)号：US20180076141A1

公开(公告)日：2018-03-15

申请号：US15816843

申请日：2017-11-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Bey WU ,  Dian-Hau CHEN ,  Jye-Yen CHENG ,  Sheng-Hsuan WEI ,  Li-Yu LEE ,  TaiYang WU

IPC: H01L23/532 ,  H01L23/522 ,  H01L21/768 ,  H01L21/027 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/033

CPC classification number: H01L23/5329 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/7682 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76843 ,  H01L23/5222 ,  H01L23/5283 ,  H01L23/53295

Abstract: In a method for manufacturing a semiconductor device, a first dielectric layer is formed over a substrate, first recesses are formed in the first dielectric layer. Metal wirings extending is a first direction are formed in the first recesses. A mask layer is formed over the metal wirings and the first dielectric layer, which includes a first opening extending in the first direction and is located above a space between adjacent two metal wirings. A first groove corresponding to the first opening is formed between the adjacent two metal wirings by etching the first dielectric layer using the mask layer as an etching mask. A second dielectric layer is formed so that a first air gap is formed in the first groove. A width of the first opening in a perpendicular direction to the first direction is smaller than a space between the adjacent two metal wirings.

公开(公告)号：US20190157204A1

公开(公告)日：2019-05-23

申请号：US16224031

申请日：2018-12-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Bey WU ,  Dian-Hau CHEN ,  Jye-Yen CHENG ,  Sheng-Hsuan WEI ,  Li-Yu LEE ,  TaiYang WU

IPC: H01L23/532 ,  H01L23/528 ,  H01L21/311 ,  H01L23/522 ,  H01L21/768

Abstract: In a method for manufacturing a semiconductor device, a first dielectric layer is formed over a substrate, first recesses are formed in the first dielectric layer. Metal wirings extending is a first direction are formed in the first recesses. A mask layer is formed over the metal wirings and the first dielectric layer, which includes a first opening extending in the first direction and is located above a space between adjacent two metal wirings. A first groove corresponding to the first opening is formed between the adjacent two metal wirings by etching the first dielectric layer using the mask layer as an etching mask. A second dielectric layer is formed so that a first air gap is formed in the first groove. A width of the first opening in a perpendicular direction to the first direction is smaller than a space between the adjacent two metal wirings.

公开(公告)号：US20170221827A1

公开(公告)日：2017-08-03

申请号：US15484344

申请日：2017-04-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Bey WU ,  Dian-Hau CHEN ,  Jye-Yen CHENG ,  Sheng-Hsuan WEI ,  Li-Yu LEE ,  TaiYang WU

IPC: H01L23/532 ,  H01L21/768 ,  H01L21/033 ,  H01L21/311 ,  H01L21/3105 ,  H01L23/528 ,  H01L21/027

CPC classification number: H01L23/5329 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/7682 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76843 ,  H01L23/5222 ,  H01L23/5283 ,  H01L23/53295

Abstract: In a method for manufacturing a semiconductor device, a first dielectric layer is formed over a substrate, first recesses are formed in the first dielectric layer. Metal wirings extending is a first direction are formed in the first recesses. A mask layer is formed over the metal wirings and the first dielectric layer, which includes a first opening extending in the first direction and is located above a space between adjacent two metal wirings. A first groove corresponding to the first opening is formed between the adjacent two metal wirings by etching the first dielectric layer using the mask layer as an etching mask. A second dielectric layer is formed so that a first air gap is formed in the first groove. A width of the first opening in a perpendicular direction to the first direction is smaller than a space between the adjacent two metal wirings.

公开(公告)号：US20250107207A1

公开(公告)日：2025-03-27

申请号：US18974319

申请日：2024-12-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Sheng LAI ,  Wei-Chung SUN ,  Yu-Bey WU ,  Yuan-Ching PENG ,  Yu-Shan LU ,  Li-Ting CHEN ,  Shih-Yao LIN ,  Yu-Fan PENG ,  Kuei-Yu KAO ,  Chih-Han LIN ,  Jing Yi YAN ,  Pei-Yi LIU

IPC: H01L29/423 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

Abstract: A semiconductor structure includes a semiconductor substrate; fin active regions protruded above the semiconductor substrate; and a gate stack disposed on the fin active regions; wherein the gate stack includes a high-k dielectric material layer, and various metal layers disposed on the high-k dielectric material layer. The gate stack has an uneven profile in a sectional view with a first dimension D1 at a top surface, a second dimension D2 at a bottom surface, and a third dimension D3 at a location between the top surface and the bottom surface, and wherein each of D1 and D2 is greater than D3.

公开(公告)号：US20210143101A1

公开(公告)日：2021-05-13

申请号：US17135791

申请日：2020-12-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Bey WU ,  Dian-Hau CHEN ,  Jye-Yen CHENG ,  Sheng-Hsuan WEI ,  Li-Yu LEE ,  TaiYang WU

IPC: H01L23/532 ,  H01L21/768 ,  H01L21/311 ,  H01L23/522 ,  H01L23/528

Abstract: In a method for manufacturing a semiconductor device, a first dielectric layer is formed over a substrate, first recesses are formed in the first dielectric layer. Metal wirings extending is a first direction are formed in the first recesses. A mask layer is formed over the metal wirings and the first dielectric layer, which includes a first opening extending in the first direction and is located above a space between adjacent two metal wirings. A first groove corresponding to the first opening is formed between the adjacent two metal wirings by etching the first dielectric layer using the mask layer as an etching mask. A second dielectric layer is formed so that a first air gap is formed in the first groove. A width of the first opening in a perpendicular direction to the first direction is smaller than a space between the adjacent two metal wirings.