公开(公告)号：US20220028744A1

公开(公告)日：2022-01-27

申请号：US16947196

申请日：2020-07-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Ju CHOU ,  Yuan-Ching PENG ,  Jiun-Ming KUO

IPC: H01L21/8234 ,  H01L21/02 ,  H01L29/66

Abstract: Methods and associated devices including the fabrication of a semiconductor structure are described that include epitaxially growing a stack of layers alternating between a first composition and a second composition. The stack of layers extends across a first region and a second region of a semiconductor substrate. The stack of layers in the second region of the semiconductor substrate may be etched to form an opening. A passivation process is then performed that includes introducing chlorine to at least one surface of the opening. After performing the passivation process, an epitaxial liner layer is grown in the opening.

公开(公告)号：US20250107207A1

公开(公告)日：2025-03-27

申请号：US18974319

申请日：2024-12-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Sheng LAI ,  Wei-Chung SUN ,  Yu-Bey WU ,  Yuan-Ching PENG ,  Yu-Shan LU ,  Li-Ting CHEN ,  Shih-Yao LIN ,  Yu-Fan PENG ,  Kuei-Yu KAO ,  Chih-Han LIN ,  Jing Yi YAN ,  Pei-Yi LIU

IPC: H01L29/423 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

Abstract: A semiconductor structure includes a semiconductor substrate; fin active regions protruded above the semiconductor substrate; and a gate stack disposed on the fin active regions; wherein the gate stack includes a high-k dielectric material layer, and various metal layers disposed on the high-k dielectric material layer. The gate stack has an uneven profile in a sectional view with a first dimension D1 at a top surface, a second dimension D2 at a bottom surface, and a third dimension D3 at a location between the top surface and the bottom surface, and wherein each of D1 and D2 is greater than D3.

公开(公告)号：US20150228791A1

公开(公告)日：2015-08-13

申请号：US14697656

申请日：2015-04-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei-Yang LEE ,  Yuan-Ching PENG ,  Chun-Hsiung TSAI

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/66 ,  H01L21/306 ,  H01L29/161 ,  H01L29/165

CPC classification number: H01L29/7848 ,  H01L21/02532 ,  H01L21/30604 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66431 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78

Abstract: A semiconductor substructure with improved performance and a method of forming the same is described. In one embodiment, the semiconductor substructure includes a substrate, having an upper surface; a gate structure formed over the substrate; a spacer formed along a sidewall of the gate structure; and a source/drain structure disposed adjacent the gate structure. The source/drain structures is formed of a strain material and is disposed in an recess that extends below the upper surface of the substrate. An interface between the spacer and the source-drain structure can be at least 2 nm above the upper surface of the substrate.

Abstract translation: 描述了具有改进性能的半导体子结构及其形成方法。 在一个实施例中，半导体子结构包括具有上表面的基板; 形成在所述基板上的栅极结构; 沿所述栅极结构的侧壁形成的间隔物; 以及邻近栅极结构设置的源极/漏极结构。 源极/漏极结构由应变材料形成，并且设置在在衬底的上表面下方延伸的凹部中。 间隔物和源极 - 漏极结构之间的界面可以在衬底的上表面上方至少2nm。

公开(公告)号：US20140197455A1

公开(公告)日：2014-07-17

申请号：US13739010

申请日：2013-01-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei-Yang LEE ,  Yuan-Ching PENG ,  Chun-Hsiung TSAI

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L21/02532 ,  H01L21/30604 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66431 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78

Abstract: A semiconductor substructure with improved performance and a method of forming the same is described. In one embodiment, the semiconductor substructure includes a substrate, having an upper surface; a gate structure formed over the substrate; a spacer formed along a sidewall of the gate structure; and a source/drain structure disposed adjacent the gate structure. The source/drain structures is formed of a strain material and is disposed in an recess that extends below the upper surface of the substrate. An interface between the spacer and the source-drain structure can be at least 2 nm above the upper surface of the substrate.

Abstract translation: 描述了具有改进性能的半导体子结构及其形成方法。 在一个实施例中，半导体子结构包括具有上表面的基板; 形成在所述基板上的栅极结构; 沿所述栅极结构的侧壁形成的间隔物; 以及邻近栅极结构设置的源极/漏极结构。 源极/漏极结构由应变材料形成，并且设置在在衬底的上表面下方延伸的凹部中。 间隔物和源极 - 漏极结构之间的界面可以在衬底的上表面上方至少2nm。

公开(公告)号：US20150115322A1

公开(公告)日：2015-04-30

申请号：US14554179

申请日：2014-11-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Kai CHEN ,  Hsien-Hsin LIN ,  Chia-Pin LIN ,  Chien-Tai CHAN ,  Yuan-Ching PENG

IPC: H01L27/092 ,  H01L29/78

CPC classification number: H01L27/0924 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7853

Abstract: A method includes forming a first fin and a second fin extending above a semiconductor substrate, with a shallow trench isolation (STI) region between them. A space is defined between the first and second fins above a top surface of the STI region. A first height is defined between the top surface of the STI region and top surfaces of the first and second fins. A flowable dielectric material is deposited into the space. The dielectric material has a top surface above the top surface of the STI region, so as to define a second height between the top surface of the dielectric material and the top surfaces of the first and second fins. The second height is less than the first height. First and second fin extensions are epitaxially formed above the dielectric, on the first and second fins, respectively, after the depositing step.

Abstract translation: 一种方法包括形成在半导体衬底之上延伸的第一鳍片和第二鳍片，在它们之间具有浅沟槽隔离（STI）区域。 在STI区域的顶表面之上的第一和第二鳍之间限定空间。 第一高度限定在STI区域的顶表面和第一鳍片和第二鳍片的顶表面之间。 可流动的电介质材料沉积到该空间中。 电介质材料具有在STI区域的顶表面上方的顶表面，以便在介电材料的顶表面和第一和第二鳍片的顶表面之间限定第二高度。 第二个高度小于第一个高度。 在沉积步骤之后，第一和第二鳍片延伸部分别外延形成在电介质上方，分别在第一和第二鳍片上。