公开(公告)号：US20190131421A1

公开(公告)日：2019-05-02

申请号：US15797973

申请日：2017-10-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiang-Ku SHEN ,  Jin-Mu YIN ,  Tsung-Chieh HSIAO ,  Chia-Lin CHUANG ,  Li-Zhen YU ,  Dian-Hau CHEN ,  Shih-Wei WANG ,  De-Wei YU ,  Chien-Hao CHEN ,  Bo-Cyuan LU ,  Jr-Hung LI ,  Chi-On CHUI ,  Min-Hsiu HUNG ,  Huang-Yi HUANG ,  Chun-Cheng CHOU ,  Ying-Liang CHUANG ,  Yen-Chun HUANG ,  Chih-Tang PENG ,  Cheng-Po CHAU ,  Yen-Ming CHEN

IPC: H01L29/66 ,  H01L21/311 ,  H01L29/78 ,  H01L21/768 ,  H01L21/3065 ,  H01L21/8234 ,  H01L29/45 ,  H01L27/088 ,  H01L29/08

Abstract: Structures and formation methods of a semiconductor device structure are provided. The method includes forming a fin structure over a substrate. The method also includes forming a gate structure over the fin structure. The method further includes forming fin spacers over sidewalls of the fin structure and gate spacers over sidewalls of the gate structure. In addition, the method includes forming a source/drain structure over the fin structure and depositing a dummy material layer to cover the source/drain structure. The dummy material layer is removed faster than the gate spacers during the removal of the dummy material layer. The method further includes forming a salicide layer over the source/drain structure and the fin spacers, and forming a contact over the salicide layer. The dummy material layer includes Ge, amorphous silicon or spin-on carbon.

公开(公告)号：US20190043763A1

公开(公告)日：2019-02-07

申请号：US15670401

申请日：2017-08-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Cheng LI ,  Chien-Hao CHEN ,  Yung-Cheng LU ,  Jr-Jung LIN ,  Chun-Hung LEE ,  Chao-Cheng CHEN

IPC: H01L21/8238 ,  H01L21/28 ,  H01L27/108 ,  H01L29/66 ,  H01L27/092

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first amorphous layer over a substrate. The substrate has a base portion and a first fin portion over the base portion, and the first amorphous layer covers the first fin portion. The method includes annealing the first amorphous layer to crystallize the first amorphous layer into a first polycrystalline layer. The method includes forming a second amorphous layer over the first polycrystalline layer. The method includes removing a first portion of the second amorphous layer and a second portion of the first polycrystalline layer under the first portion. The remaining second amorphous layer and the remaining first polycrystalline layer together form a first gate structure over and across the first fin portion.

公开(公告)号：US20190319113A1

公开(公告)日：2019-10-17

申请号：US15952512

申请日：2018-04-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： De-Wei YU ,  Chien-Hao CHEN

IPC: H01L29/66 ,  H01L21/28

Abstract: Embodiments disclosed herein relate generally to forming a gate layer in high aspect ratio trenches using a cyclic deposition-etch process. In an embodiment, a method for semiconductor processing is provided. The method includes performing a cyclic deposition-etch process to form a conformal film over a bottom surface and along sidewall surfaces of a feature on a substrate. The method includes forming a dielectric cap layer on the conformal film. The method includes performing an anneal process on the conformal film.