公开(公告)号：US20200335388A1

公开(公告)日：2020-10-22

申请号：US16921015

申请日：2020-07-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Teng-Chun TSAI ,  Bing-Hung CHEN ,  Chien-Hsun WANG ,  Cheng-Tung LIN ,  Chih-Tang PENG ,  De-Fang CHEN ,  Huan-Just LIN ,  Li-Ting WANG ,  Yung-Cheng LU

IPC: H01L21/762 ,  H01L21/3105 ,  H01L29/78 ,  H01L29/66 ,  H01L21/311 ,  B82Y10/00 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/775 ,  H01L29/06 ,  H01L29/41

Abstract: According to an exemplary embodiment, a method of forming an isolation layer is provided. The method includes the following operations: providing a substrate; providing a vertical structure having a first layer over the substrate; providing a first interlayer dielectric over the first layer; performing CMP on the first interlayer dielectric; and etching back the first interlayer dielectric and the first layer to form the isolation layer corresponding to a source of the vertical structure.

公开(公告)号：US20180240882A1

公开(公告)日：2018-08-23

申请号：US15959900

申请日：2018-04-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Tang PENG ,  Tai-Chun HUANG ,  Teng-Chun TSAI ,  Cheng-Tung LIN ,  De-Fang CHEN ,  Li-Ting WANG ,  Chien-Hsun WANG ,  Huan-Just LIN ,  Yung-Cheng LU ,  Tze-Liang LEE

IPC: H01L29/423 ,  H01L21/02 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L23/31 ,  H01L23/00 ,  B82Y40/00 ,  B82Y10/00 ,  H01L23/29 ,  H01L29/788 ,  H01L29/775 ,  H01L27/088

CPC classification number: H01L29/42392 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02126 ,  H01L21/02167 ,  H01L21/0217 ,  H01L23/291 ,  H01L23/3171 ,  H01L23/564 ,  H01L27/088 ,  H01L29/0676 ,  H01L29/42356 ,  H01L29/66272 ,  H01L29/66439 ,  H01L29/66666 ,  H01L29/775 ,  H01L29/7827 ,  H01L29/7889 ,  H01L2924/0002 ,  H01L2924/00

Abstract: According to an exemplary embodiment, a method of forming a vertical structure with at least two barrier layers is provided. The method includes the following operations: providing a substrate; providing a vertical structure over the substrate; providing a first barrier layer over a source, a channel, and a drain of the vertical structure; and providing a second barrier layer over a gate and the drain of the vertical structure.

公开(公告)号：US20190043763A1

公开(公告)日：2019-02-07

申请号：US15670401

申请日：2017-08-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Cheng LI ,  Chien-Hao CHEN ,  Yung-Cheng LU ,  Jr-Jung LIN ,  Chun-Hung LEE ,  Chao-Cheng CHEN

IPC: H01L21/8238 ,  H01L21/28 ,  H01L27/108 ,  H01L29/66 ,  H01L27/092

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first amorphous layer over a substrate. The substrate has a base portion and a first fin portion over the base portion, and the first amorphous layer covers the first fin portion. The method includes annealing the first amorphous layer to crystallize the first amorphous layer into a first polycrystalline layer. The method includes forming a second amorphous layer over the first polycrystalline layer. The method includes removing a first portion of the second amorphous layer and a second portion of the first polycrystalline layer under the first portion. The remaining second amorphous layer and the remaining first polycrystalline layer together form a first gate structure over and across the first fin portion.

公开(公告)号：US20170190017A1

公开(公告)日：2017-07-06

申请号：US14985173

申请日：2015-12-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Teng-Chun TSAI ,  Shen-Nan LEE ,  Yung-Cheng LU ,  Chia-Chiung LO ,  Shwang-Ming JENG ,  Yee-Chia YEO

IPC: B24B37/20

CPC classification number: B24B37/20

Abstract: A polisher includes a wafer carrier, a polishing head, a movement mechanism, and a rotation mechanism. The wafer carrier has a supporting surface. The supporting surface is configured to carry a wafer thereon. The polishing head is present above the wafer carrier. The polishing head has a polishing surface. The polishing surface of the polishing head is smaller than the supporting surface of the wafer carrier. The movement mechanism is configured to move the polishing head relative to the wafer carrier. The rotation mechanism is configured to rotate the polishing head relative to the wafer carrier.

公开(公告)号：US20210343709A1

公开(公告)日：2021-11-04

申请号：US16863371

申请日：2020-04-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chieh-Ping WANG ,  Tai-Chun HUANG ,  Yung-Cheng LU ,  Ting-Gang CHEN ,  Chi On CHUI

IPC: H01L27/088 ,  H01L27/092 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/105

Abstract: A semiconductor device with isolation structures of different dielectric constants and a method of fabricating the same are disclosed. The semiconductor device includes fin structures with first and second fin portions disposed on first and second device areas on a substrate and first and second pair of gate structures disposed on the first and second fin portions. The second pair of gate structures is electrically isolated from the first pair of gate structures. The semiconductor device further includes a first isolation structure interposed between the first pair of gate structures and a second isolation structure interposed between the second pair of gate structures. The first isolation structure includes a first nitride liner and a first oxide fill layer. The second isolation structure includes a second nitride liner and a second oxide fill layer. The second nitride liner is thicker than the first nitride liner.

公开(公告)号：US20180350655A1

公开(公告)日：2018-12-06

申请号：US16049520

申请日：2018-07-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Teng-Chun TSAI ,  Bing-Hung CHEN ,  Chien-Hsun WANG ,  Cheng-Tung LIN ,  Chih-Tang PENG ,  De-Fang CHEN ,  Huan-Just LIN ,  Li-Ting WANG ,  Yung-Cheng LU

IPC: H01L21/762 ,  H01L21/3105 ,  H01L29/41 ,  H01L29/06 ,  H01L29/775 ,  H01L29/423 ,  H01L21/8238 ,  B82Y10/00 ,  H01L21/311 ,  H01L29/66

Abstract: According to an exemplary embodiment, a method of forming an isolation layer is provided. The method includes the following operations: providing a substrate; providing a vertical structure having a first layer over the substrate; providing a first interlayer dielectric over the first layer; performing CMP on the first interlayer dielectric; and etching back the first interlayer dielectric and the first layer to form the isolation layer corresponding to a source of the vertical structure.