公开(公告)号：US20230238443A1

公开(公告)日：2023-07-27

申请号：US18129961

申请日：2023-04-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Ming LIN ,  Sai-Hooi YEONG ,  Ziwei FANG ,  Chi On CHUI ,  Huang-Lin CHAO

IPC: H01L29/51 ,  H01L29/78 ,  H01L21/02 ,  H01L21/28 ,  H01L29/66 ,  H01L27/088

CPC classification number: H01L29/516 ,  H01L29/7851 ,  H01L21/02356 ,  H01L21/28176 ,  H01L29/66795 ,  H01L27/0886 ,  H01L29/6684 ,  H01L29/78391 ,  H01L29/785

Abstract: The present disclosure describes a device that is protected from the effects of an oxide on the metal gate layers of ferroelectric field effect transistors. In some embodiments, the device includes a substrate with fins thereon; an interfacial layer on the fins; a crystallized ferroelectric layer on the interfacial layer; and a metal gate layer on the ferroelectric layer,

公开(公告)号：US20210083068A1

公开(公告)日：2021-03-18

申请号：US16573498

申请日：2019-09-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Ming LIN ,  Sai-Hooi YEONG ,  Ziwei FANG ,  Chi On CHUI ,  Huang-Lin CHAO

IPC: H01L29/51 ,  H01L29/78 ,  H01L29/66 ,  H01L21/28 ,  H01L21/02

Abstract: The present disclosure describes a method that can eliminate or minimize the formation of an oxide on the metal gate layers of ferroelectric field effect transistors. In some embodiments, the method includes providing a substrate with fins thereon; depositing an interfacial layer on the fins; depositing a ferroelectric layer on the interfacial layer; depositing a metal gate layer on the ferroelectric layer; exposing the metal gate layer to a metal-halide gas; and performing a post metallization annealing, where the exposing the metal gate layer to the metal-halide gas and the performing the post metallization annealing occur without a vacuum break.

公开(公告)号：US20200161240A1

公开(公告)日：2020-05-21

申请号：US16722630

申请日：2019-12-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ta YU ,  Kai-Hsuan LEE ,  Yen-Ming CHEN ,  Chi On CHUI ,  Sai-Hooi YEONG

IPC: H01L23/528 ,  H01L21/3105 ,  H01L23/532 ,  H01L23/522 ,  H01L21/768 ,  H01L21/02 ,  C23C16/34 ,  C23C16/04 ,  C23C16/02 ,  C23C14/06 ,  C23C14/04 ,  C23C14/02

Abstract: Methods and devices for forming a conductive line disposed over a substrate. A first dielectric layer is disposed over the substrate and coplanar with the conductive line. A second dielectric layer disposed over the conductive line and a third dielectric layer disposed over the first dielectric layer. A via extends through the second dielectric layer and is coupled to the conductive line. The second dielectric layer and the third dielectric layer are coplanar and the second and third dielectric layers have a different composition. In some embodiments, the second dielectric layer is selectively deposited on the conductive line.

公开(公告)号：US20190123161A1

公开(公告)日：2019-04-25

申请号：US16228872

申请日：2018-12-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yee-Chia YEO ,  Sung-Li WANG ,  Chi On CHUI ,  Jyh-Cherng SHEU ,  Hung-Li CHIANG ,  I-Sheng CHEN

IPC: H01L29/45 ,  H01L27/092 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/417 ,  H01L29/08 ,  H01L21/8238 ,  H01L29/78 ,  H01L23/522

CPC classification number: H01L29/45 ,  H01L21/823425 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L23/5226 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/456 ,  H01L29/7851 ,  H01L2029/7858

Abstract: A semiconductor device includes a field effect transistor (FET). The FET includes a first channel, a first source and a first drain; a second channel, a second source and a second drain; and a gate structure disposed over the first and second channels. The gate structure includes a gate dielectric layer and a gate electrode layer. The first source includes a first crystal semiconductor layer and the second source includes a second crystal semiconductor layer. The first source and the second source are connected by an alloy layer made of one or more Group IV element and one or more transition metal elements. The first crystal semiconductor layer is not in direct contact with the second crystal semiconductor layer.

公开(公告)号：US20240186414A1

公开(公告)日：2024-06-06

申请号：US18402455

申请日：2024-01-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ming LIN ,  Sai-Hooi YEONG ,  Ziwei FANG ,  Bo-Feng YOUNG ,  Chi On CHUI ,  Chih-Yu CHANG ,  Huang-Lin CHAO

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/28 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L29/78391 ,  H01L21/02181 ,  H01L21/0234 ,  H01L21/02356 ,  H01L29/40111 ,  H01L29/516 ,  H01L29/66795 ,  H01L29/6684 ,  H01L29/7851

Abstract: The present disclosure relates to a semiconductor device includes a substrate and first and second spacers on the substrate. The semiconductor device includes a gate stack between the first and second spacers. The gate stack includes a gate dielectric layer having a first portion formed on the substrate and a second portion formed on the first and second spacers. The first portion includes a crystalline material and the second portion comprises an amorphous material. The gate stack further includes a gate electrode on the first and second portions of the gate dielectric layer.

公开(公告)号：US20210376138A1

公开(公告)日：2021-12-02

申请号：US16887203

申请日：2020-05-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi LEE ,  Cheng-Lung HUNG ,  Ji-Cheng CHEN ,  Weng CHANG ,  Chi On CHUI

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/66

Abstract: A semiconductor device with different gate structure configurations and a method of fabricating the same are disclosed. The semiconductor device includes a fin structure disposed on a substrate, a nanostructured channel region disposed on the fin structure, and a gate-all-around (GAA) structure surrounding the nanostructured channel region. The GAA structure includes a high-K (HK) gate dielectric layer with a metal doped region having dopants of a first metallic material, a p-type work function metal (pWFM) layer disposed on the HK gate dielectric layer, a bimetallic nitride layer interposed between the HK gate dielectric layer and the pWFM layer, an n-type work function metal (nWFM) layer disposed on the pWFM layer, and a gate metal fill layer disposed on the nWFM layer. The pWFM layer includes a second metallic material and the bimetallic nitride layer includes the first and second metallic materials.

公开(公告)号：US20210343709A1

公开(公告)日：2021-11-04

申请号：US16863371

申请日：2020-04-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chieh-Ping WANG ,  Tai-Chun HUANG ,  Yung-Cheng LU ,  Ting-Gang CHEN ,  Chi On CHUI

IPC: H01L27/088 ,  H01L27/092 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/105

Abstract: A semiconductor device with isolation structures of different dielectric constants and a method of fabricating the same are disclosed. The semiconductor device includes fin structures with first and second fin portions disposed on first and second device areas on a substrate and first and second pair of gate structures disposed on the first and second fin portions. The second pair of gate structures is electrically isolated from the first pair of gate structures. The semiconductor device further includes a first isolation structure interposed between the first pair of gate structures and a second isolation structure interposed between the second pair of gate structures. The first isolation structure includes a first nitride liner and a first oxide fill layer. The second isolation structure includes a second nitride liner and a second oxide fill layer. The second nitride liner is thicker than the first nitride liner.

公开(公告)号：US20190067194A1

公开(公告)日：2019-02-28

申请号：US15692439

申请日：2017-08-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ta YU ,  Kai-Hsuan LEE ,  Yen-Ming CHEN ,  Chi On CHUI ,  Sai-Hooi YEONG

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768

Abstract: Methods and devices for forming a conductive line disposed over a substrate. A first dielectric layer is disposed over the substrate and coplanar with the conductive line. A second dielectric layer disposed over the conductive line and a third dielectric layer disposed over the first dielectric layer. A via extends through the second dielectric layer and is coupled to the conductive line. The second dielectric layer and the third dielectric layer are coplanar and the second and third dielectric layers have a different composition. In some embodiments, the second dielectric layer is selectively deposited on the conductive line.

公开(公告)号：US20210020786A1

公开(公告)日：2021-01-21

申请号：US16515898

申请日：2019-07-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ming LIN ,  Sai-Hooi YEONG ,  Ziwei FANG ,  Bo-Feng YOUNG ,  Chi On CHUI ,  Chih-Yu CHANG ,  Huang-Lin CHAO

IPC: H01L29/78 ,  H01L29/51 ,  H01L21/02 ,  H01L21/28 ,  H01L29/66

Abstract: The present disclosure relates to a semiconductor device includes a substrate and first and second spacers on the substrate. The semiconductor device includes a gate stack between the first and second spacers. The gate stack includes a gate dielectric layer having a first portion formed on the substrate and a second portion formed on the first and second spacers. The first portion includes a crystalline material and the second portion comprises an amorphous material. The gate stack further includes a gate electrode on the first and second portions of the gate dielectric layer,

公开(公告)号：US20200212191A1

公开(公告)日：2020-07-02

申请号：US16814154

申请日：2020-03-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yee-Chia YEO ,  Sung-Li WANG ,  Chi On CHUI ,  Jyh-Cherng SHEU ,  Hung-Li CHIANG ,  I-Sheng CHEN

IPC: H01L29/45 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/8234 ,  H01L23/522 ,  H01L27/088 ,  H01L29/08 ,  H01L29/417 ,  H01L29/78

Abstract: A semiconductor device includes a field effect transistor (FET). The FET includes a first channel, a first source and a first drain; a second channel, a second source and a second drain; and a gate structure disposed over the first and second channels. The gate structure includes a gate dielectric layer and a gate electrode layer. The first source includes a first crystal semiconductor layer and the second source includes a second crystal semiconductor layer. The first source and the second source are connected by an alloy layer made of one or more Group IV element and one or more transition metal elements. The first crystal semiconductor layer is not in direct contact with the second crystal semiconductor layer.