公开(公告)号：US20190148519A1

公开(公告)日：2019-05-16

申请号：US15875485

申请日：2018-01-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kai-Hsuan LEE ,  Bo-Yu LAI ,  Chi-On CHUI ,  Cheng-Yu YANG ,  Yen-Ting CHEN ,  Sai-Hooi YEONG ,  Feng-Cheng YANG ,  Yen-Ming CHEN

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L29/417 ,  H01L21/306 ,  H01L21/762

Abstract: A semiconductor device and a method for forming the same are provided. The method includes forming a gate structure over a fin structure. The method further includes forming first gate spacers on opposite sidewalls of the gate structure. The method further includes forming source/drain features in the fin structure and adjacent to the first gate spacers. The method further includes performing a surface treatment process on top surfaces of the source/drain features and outer sidewalls of the first gate spacers. The method further includes depositing a contact etch stop layer (CESL) over the source/drain features and the first gate spacers. A first portion of the CESL is deposited over the top surfaces of the source/drain features at a first deposition rate. A second portion of the CESL is deposited over the outer sidewalls of the first gate spacers at a second deposition rate.

公开(公告)号：US20160240536A1

公开(公告)日：2016-08-18

申请号：US14621814

申请日：2015-02-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD

Inventor： Kai-Hsuan LEE ,  Cheng-Yu YANG ,  Hsiang-Ku SHEN ,  Han-Ting TSAI ,  Yimin HUANG

IPC: H01L27/092 ,  H01L21/266 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/207 ,  H01L29/36

CPC classification number: H01L29/7848 ,  H01L21/823814 ,  H01L21/823871 ,  H01L27/092 ,  H01L29/161 ,  H01L29/267 ,  H01L29/495 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a first gate stack and a second gate stack over the semiconductor substrate. The semiconductor device structure also includes a first doped structure over the semiconductor substrate and adjacent to the first gate stack. The first doped structure includes a III-V compound semiconductor material and a dopant. The semiconductor device structure further includes a second doped structure over the semiconductor substrate and adjacent to the second gate stack. The second doped structure includes the III-V compound semiconductor material and the dopant. One of the first doped structure and the second doped structure is an n-type semiconductor structure, and the other one of the first doped structure and the second doped structure is a p-type semiconductor structure.

Abstract translation: 提供半导体器件结构的结构和形成方法。 半导体器件结构包括半导体衬底和半导体衬底上的第一栅极堆叠和第二栅极堆叠。 半导体器件结构还包括在半导体衬底上并与第一栅极叠层相邻的第一掺杂结构。 第一掺杂结构包括III-V族化合物半导体材料和掺杂剂。 半导体器件结构还包括在半导体衬底上并与第二栅极堆叠相邻的第二掺杂结构。 第二掺杂结构包括III-V族化合物半导体材料和掺杂剂。 第一掺杂结构和第二掺杂结构之一是n型半导体结构，第一掺杂结构和第二掺杂结构中的另一个是p型半导体结构。

公开(公告)号：US20210118749A1

公开(公告)日：2021-04-22

申请号：US17113209

申请日：2020-12-07

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Bo-Yu LAI ,  Kai-Hsuan LEE ,  Wei-Yang LEE ,  Feng-Cheng YANG ,  Yen-Ming CHEN

IPC: H01L21/8238 ,  H01L29/66 ,  H01L29/06 ,  H01L27/092 ,  H01L29/78 ,  H01L21/8234

Abstract: A semiconductor device includes a gate stack, an epitaxy structure, a first spacer, a second spacer, and a dielectric residue. The gate stack is over a substrate. The epitaxy structure is formed raised above the substrate. The first spacer is on a sidewall of the gate stack. The first spacer and the epitaxy structure define an air gap therebetween. The second spacer seals the air gap between the first spacer and the epitaxy structure. The dielectric residue is in the air gap and has an upper portion and a lower portion under the upper portion. The upper portion of the dielectric residue has higher etch resistance to phosphoric acid than that of the lower portion of the dielectric residue.

公开(公告)号：US20190067197A1

公开(公告)日：2019-02-28

申请号：US16048957

申请日：2018-07-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ta YU ,  Kai-Hsuan LEE ,  Yen-Ming CHEN ,  Chi On CHUI ,  Sai-Hooi YEONG

IPC: H01L23/528 ,  H01L23/532 ,  C23C14/02 ,  H01L21/768 ,  H01L21/288 ,  H01L21/02 ,  C23C16/34 ,  C23C16/04 ,  C23C16/02 ,  C23C14/06 ,  C23C14/04 ,  H01L23/522

Abstract: Methods and devices for forming a conductive line disposed over a substrate. A first dielectric layer is disposed over the substrate and coplanar with the conductive line. A second dielectric layer disposed over the conductive line and a third dielectric layer disposed over the first dielectric layer. A via extends through the second dielectric layer and is coupled to the conductive line. The second dielectric layer and the third dielectric layer are coplanar and the second and third dielectric layers have a different composition. In some embodiments, the second dielectric layer is selectively deposited on the conductive line.

公开(公告)号：US20190067012A1

公开(公告)日：2019-02-28

申请号：US15692221

申请日：2017-08-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-An LIN ,  Chun-Hsiung LIN ,  Kai-Hsuan LEE ,  Sai-Hooi YEONG ,  Cheng-Yu YANG ,  Yen-Ting CHEN

IPC: H01L21/285 ,  H01L21/768

Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a semiconductor substrate, a gate structure, a first doped structure, a second doped structure, and a dielectric layer. The method includes forming a through hole in the dielectric layer. The method includes performing a physical vapor deposition process to deposit a first metal layer over the first doped structure exposed by the through hole. The method includes reacting the first metal layer with the first doped structure to form a metal semiconductor compound layer between the first metal layer and the first doped structure. The method includes removing the first metal layer. The method includes performing a chemical vapor deposition process to deposit a second metal layer in the through hole. The method includes forming a conductive structure in the through hole and over the second metal layer.

公开(公告)号：US20240112958A1

公开(公告)日：2024-04-04

申请号：US18526828

申请日：2023-12-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sai-Hooi YEONG ,  Kai-Hsuan LEE

IPC: H01L21/8238 ,  H01L21/768 ,  H01L27/092 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823871 ,  H01L21/7682 ,  H01L21/76897 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/66795 ,  H01L29/7851

Abstract: A method of forming a device includes providing a transistor having a gate structure and a source/drain structure adjacent to the gate structure. A cavity is formed along a sidewall surface of a contact opening over the source/drain structure. After forming the cavity, a sacrificial layer is deposited over a bottom surface and along the sidewall surface of the contact opening including within the cavity. A first portion of the sacrificial layer along the bottom surface of the contact opening is removed to expose a portion of the source/drain structure. A metal plug is then formed over the portion of the exposed source/drain structure. A remaining portion of the sacrificial layer is removed to form an air gap disposed between the metal plug and the gate structure. Thereafter, a seal layer is deposited over the air gap to form an air gap spacer.

公开(公告)号：US20210225713A1

公开(公告)日：2021-07-22

申请号：US17222739

申请日：2021-04-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sai-Hooi YEONG ,  Kai-Hsuan LEE

IPC: H01L21/8238 ,  H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L21/768 ,  H01L27/092

Abstract: A method of forming a device includes providing a transistor having a gate structure and a source/drain structure adjacent to the gate structure. A cavity is formed along a sidewall surface of a contact opening over the source/drain structure. After forming the cavity, a sacrificial layer is deposited over a bottom surface and along the sidewall surface of the contact opening including within the cavity. A first portion of the sacrificial layer along the bottom surface of the contact opening is removed to expose a portion of the source/drain structure. A metal plug is then formed over the portion of the exposed source/drain structure. A remaining portion of the sacrificial layer is removed to form an air gap disposed between the metal plug and the gate structure. Thereafter, a seal layer is deposited over the air gap to form an air gap spacer.

公开(公告)号：US20190067194A1

公开(公告)日：2019-02-28

申请号：US15692439

申请日：2017-08-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ta YU ,  Kai-Hsuan LEE ,  Yen-Ming CHEN ,  Chi On CHUI ,  Sai-Hooi YEONG

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768

Abstract: Methods and devices for forming a conductive line disposed over a substrate. A first dielectric layer is disposed over the substrate and coplanar with the conductive line. A second dielectric layer disposed over the conductive line and a third dielectric layer disposed over the first dielectric layer. A via extends through the second dielectric layer and is coupled to the conductive line. The second dielectric layer and the third dielectric layer are coplanar and the second and third dielectric layers have a different composition. In some embodiments, the second dielectric layer is selectively deposited on the conductive line.

公开(公告)号：US20170207095A1

公开(公告)日：2017-07-20

申请号：US14996031

申请日：2016-01-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kai-Hsuan LEE ,  Jyh-Cherng SHEU ,  Sung-Li WANG ,  Cheng-Yu YANG ,  Sheng-Chen WANG ,  Sai-Hooi YEONG

IPC: H01L21/285 ,  H01L29/08 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L21/768

CPC classification number: H01L21/28518 ,  H01L21/76843 ,  H01L21/76855 ,  H01L23/485 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66795

Abstract: In a method of manufacturing a semiconductor device, a first layer containing an amorphous first material is formed by a deposition process over a semiconductor layer. A second layer containing a metal second material is formed over the first layer. A thermal process is performed to form an alloy layer of the amorphous first material and the metal second material.

公开(公告)号：US20170125304A1

公开(公告)日：2017-05-04

申请号：US15242155

申请日：2016-08-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Sheng-Chen WANG ,  Kai-Hsuan LEE ,  Sai-Hooi YEONG ,  Chia-Ta YU

IPC: H01L21/8238 ,  H01L29/10 ,  H01L27/092 ,  H01L21/762 ,  H01L21/02

CPC classification number: H01L21/823821 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/76224 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/1054 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: In manufacturing a semiconductor device, a stack of first and second semiconductor layers are formed. A fin structure is formed by patterning the first and second semiconductor layers. A cover layer is formed on a bottom part of the fin structure so as to cover side walls of the bottom portion of the fin structure and a bottom part of side walls of the upper portion of the fin structure. An insulating layer is formed so that the fin structure is embedded in the insulating layer. A part of the upper portion is removed so that an opening is formed in the insulating layer. A third semiconductor layer is formed in the opening on the remaining layer of the second semiconductor layer. The insulating layer is recessed so that a part of the third semiconductor layer is exposed from the insulating layer, and a gate structure is formed.